cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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entry.h (2527B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2
      3#ifndef __ASM_CSKY_ENTRY_H
      4#define __ASM_CSKY_ENTRY_H
      5
      6#include <asm/setup.h>
      7#include <abi/regdef.h>
      8
      9#define LSAVE_PC	8
     10#define LSAVE_PSR	12
     11#define LSAVE_A0	24
     12#define LSAVE_A1	28
     13#define LSAVE_A2	32
     14#define LSAVE_A3	36
     15#define LSAVE_A4	40
     16#define LSAVE_A5	44
     17
     18#define usp ss1
     19
     20.macro USPTOKSP
     21	mtcr	sp, usp
     22	mfcr	sp, ss0
     23.endm
     24
     25.macro KSPTOUSP
     26	mtcr	sp, ss0
     27	mfcr	sp, usp
     28.endm
     29
     30.macro	SAVE_ALL epc_inc
     31	mtcr    r13, ss2
     32	mfcr    r13, epsr
     33	btsti   r13, 31
     34	bt      1f
     35	USPTOKSP
     361:
     37	subi    sp, 32
     38	subi    sp, 32
     39	subi    sp, 16
     40	stw     r13, (sp, 12)
     41
     42	stw     lr, (sp, 4)
     43
     44	mfcr	lr, epc
     45	movi	r13, \epc_inc
     46	add	lr, r13
     47	stw     lr, (sp, 8)
     48
     49	mov	lr, sp
     50	addi	lr, 32
     51	addi	lr, 32
     52	addi	lr, 16
     53	bt	2f
     54	mfcr	lr, ss1
     552:
     56	stw     lr, (sp, 16)
     57
     58	stw     a0, (sp, 20)
     59	stw     a0, (sp, 24)
     60	stw     a1, (sp, 28)
     61	stw     a2, (sp, 32)
     62	stw     a3, (sp, 36)
     63
     64	addi	sp, 32
     65	addi	sp, 8
     66	mfcr    r13, ss2
     67	stw	r6, (sp)
     68	stw	r7, (sp, 4)
     69	stw	r8, (sp, 8)
     70	stw	r9, (sp, 12)
     71	stw	r10, (sp, 16)
     72	stw	r11, (sp, 20)
     73	stw	r12, (sp, 24)
     74	stw	r13, (sp, 28)
     75	stw	r14, (sp, 32)
     76	stw	r1, (sp, 36)
     77	subi	sp, 32
     78	subi	sp, 8
     79.endm
     80
     81.macro	RESTORE_ALL
     82	ldw	lr, (sp, 4)
     83	ldw     a0, (sp, 8)
     84	mtcr    a0, epc
     85	ldw     a0, (sp, 12)
     86	mtcr    a0, epsr
     87	btsti   a0, 31
     88	bt      1f
     89	ldw     a0, (sp, 16)
     90	mtcr	a0, ss1
     911:
     92	ldw     a0, (sp, 24)
     93	ldw     a1, (sp, 28)
     94	ldw     a2, (sp, 32)
     95	ldw     a3, (sp, 36)
     96
     97	addi	sp, 32
     98	addi	sp, 8
     99	ldw	r6, (sp)
    100	ldw	r7, (sp, 4)
    101	ldw	r8, (sp, 8)
    102	ldw	r9, (sp, 12)
    103	ldw	r10, (sp, 16)
    104	ldw	r11, (sp, 20)
    105	ldw	r12, (sp, 24)
    106	ldw	r13, (sp, 28)
    107	ldw	r14, (sp, 32)
    108	ldw	r1, (sp, 36)
    109	addi	sp, 32
    110	addi	sp, 8
    111
    112	bt      2f
    113	KSPTOUSP
    1142:
    115	rte
    116.endm
    117
    118.macro SAVE_SWITCH_STACK
    119	subi    sp, 32
    120	stm     r8-r15, (sp)
    121.endm
    122
    123.macro RESTORE_SWITCH_STACK
    124	ldm     r8-r15, (sp)
    125	addi    sp, 32
    126.endm
    127
    128/* MMU registers operators. */
    129.macro RD_MIR	rx
    130	cprcr   \rx, cpcr0
    131.endm
    132
    133.macro RD_MEH	rx
    134	cprcr   \rx, cpcr4
    135.endm
    136
    137.macro RD_MCIR	rx
    138	cprcr   \rx, cpcr8
    139.endm
    140
    141.macro RD_PGDR  rx
    142	cprcr   \rx, cpcr29
    143.endm
    144
    145.macro WR_MEH	rx
    146	cpwcr   \rx, cpcr4
    147.endm
    148
    149.macro WR_MCIR	rx
    150	cpwcr   \rx, cpcr8
    151.endm
    152
    153.macro SETUP_MMU
    154	/* Init psr and enable ee */
    155	lrw	r6, DEFAULT_PSR_VALUE
    156	mtcr    r6, psr
    157	psrset  ee
    158
    159	/* Select MMU as co-processor */
    160	cpseti	cp15
    161
    162	/*
    163	 * cpcr30 format:
    164	 * 31 - 29 | 28 - 4 | 3 | 2 | 1 | 0
    165	 *   BA     Reserved  C   D   V
    166	 */
    167	cprcr	r6, cpcr30
    168	lsri	r6, 29
    169	lsli	r6, 29
    170	addi	r6, 0xe
    171	cpwcr	r6, cpcr30
    172
    173	movi	r6, 0
    174	cpwcr	r6, cpcr31
    175.endm
    176#endif /* __ASM_CSKY_ENTRY_H */