fpu.h (2271B)
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2#ifndef _ASM_IA64_FPU_H 3#define _ASM_IA64_FPU_H 4 5/* 6 * Copyright (C) 1998, 1999, 2002, 2003 Hewlett-Packard Co 7 * David Mosberger-Tang <davidm@hpl.hp.com> 8 */ 9 10#include <linux/types.h> 11 12/* floating point status register: */ 13#define FPSR_TRAP_VD (1 << 0) /* invalid op trap disabled */ 14#define FPSR_TRAP_DD (1 << 1) /* denormal trap disabled */ 15#define FPSR_TRAP_ZD (1 << 2) /* zero-divide trap disabled */ 16#define FPSR_TRAP_OD (1 << 3) /* overflow trap disabled */ 17#define FPSR_TRAP_UD (1 << 4) /* underflow trap disabled */ 18#define FPSR_TRAP_ID (1 << 5) /* inexact trap disabled */ 19#define FPSR_S0(x) ((x) << 6) 20#define FPSR_S1(x) ((x) << 19) 21#define FPSR_S2(x) (__IA64_UL(x) << 32) 22#define FPSR_S3(x) (__IA64_UL(x) << 45) 23 24/* floating-point status field controls: */ 25#define FPSF_FTZ (1 << 0) /* flush-to-zero */ 26#define FPSF_WRE (1 << 1) /* widest-range exponent */ 27#define FPSF_PC(x) (((x) & 0x3) << 2) /* precision control */ 28#define FPSF_RC(x) (((x) & 0x3) << 4) /* rounding control */ 29#define FPSF_TD (1 << 6) /* trap disabled */ 30 31/* floating-point status field flags: */ 32#define FPSF_V (1 << 7) /* invalid operation flag */ 33#define FPSF_D (1 << 8) /* denormal/unnormal operand flag */ 34#define FPSF_Z (1 << 9) /* zero divide (IEEE) flag */ 35#define FPSF_O (1 << 10) /* overflow (IEEE) flag */ 36#define FPSF_U (1 << 11) /* underflow (IEEE) flag */ 37#define FPSF_I (1 << 12) /* inexact (IEEE) flag) */ 38 39/* floating-point rounding control: */ 40#define FPRC_NEAREST 0x0 41#define FPRC_NEGINF 0x1 42#define FPRC_POSINF 0x2 43#define FPRC_TRUNC 0x3 44 45#define FPSF_DEFAULT (FPSF_PC (0x3) | FPSF_RC (FPRC_NEAREST)) 46 47/* This default value is the same as HP-UX uses. Don't change it 48 without a very good reason. */ 49#define FPSR_DEFAULT (FPSR_TRAP_VD | FPSR_TRAP_DD | FPSR_TRAP_ZD \ 50 | FPSR_TRAP_OD | FPSR_TRAP_UD | FPSR_TRAP_ID \ 51 | FPSR_S0 (FPSF_DEFAULT) \ 52 | FPSR_S1 (FPSF_DEFAULT | FPSF_TD | FPSF_WRE) \ 53 | FPSR_S2 (FPSF_DEFAULT | FPSF_TD) \ 54 | FPSR_S3 (FPSF_DEFAULT | FPSF_TD)) 55 56# ifndef __ASSEMBLY__ 57 58struct ia64_fpreg { 59 union { 60 unsigned long bits[2]; 61 long double __dummy; /* force 16-byte alignment */ 62 } u; 63}; 64 65# endif /* __ASSEMBLY__ */ 66 67#endif /* _ASM_IA64_FPU_H */