cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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esi_stub.S (3005B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * ESI call stub.
      4 *
      5 * Copyright (C) 2005 Hewlett-Packard Co
      6 *	Alex Williamson <alex.williamson@hp.com>
      7 *
      8 * Based on EFI call stub by David Mosberger.  The stub is virtually
      9 * identical to the one for EFI phys-mode calls, except that ESI
     10 * calls may have up to 8 arguments, so they get passed to this routine
     11 * through memory.
     12 *
     13 * This stub allows us to make ESI calls in physical mode with interrupts
     14 * turned off.  ESI calls may not support calling from virtual mode.
     15 *
     16 * Google for "Extensible SAL specification" for a document describing the
     17 * ESI standard.
     18 */
     19
     20/*
     21 * PSR settings as per SAL spec (Chapter 8 in the "IA-64 System
     22 * Abstraction Layer Specification", revision 2.6e).  Note that
     23 * psr.dfl and psr.dfh MUST be cleared, despite what this manual says.
     24 * Otherwise, SAL dies whenever it's trying to do an IA-32 BIOS call
     25 * (the br.ia instruction fails unless psr.dfl and psr.dfh are
     26 * cleared).  Fortunately, SAL promises not to touch the floating
     27 * point regs, so at least we don't have to save f2-f127.
     28 */
     29#define PSR_BITS_TO_CLEAR						\
     30	(IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_RT |		\
     31	 IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED |	\
     32	 IA64_PSR_DFL | IA64_PSR_DFH)
     33
     34#define PSR_BITS_TO_SET							\
     35	(IA64_PSR_BN)
     36
     37#include <asm/processor.h>
     38#include <asm/asmmacro.h>
     39#include <asm/export.h>
     40
     41/*
     42 * Inputs:
     43 *	in0 = address of function descriptor of ESI routine to call
     44 *	in1 = address of array of ESI parameters
     45 *
     46 * Outputs:
     47 *	r8 = result returned by called function
     48 */
     49GLOBAL_ENTRY(esi_call_phys)
     50	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
     51	alloc loc1=ar.pfs,2,7,8,0
     52	ld8 r2=[in0],8			// load ESI function's entry point
     53	mov loc0=rp
     54	.body
     55	;;
     56	ld8 out0=[in1],8		// ESI params loaded from array
     57	;;				// passing all as inputs doesn't work
     58	ld8 out1=[in1],8
     59	;;
     60	ld8 out2=[in1],8
     61	;;
     62	ld8 out3=[in1],8
     63	;;
     64	ld8 out4=[in1],8
     65	;;
     66	ld8 out5=[in1],8
     67	;;
     68	ld8 out6=[in1],8
     69	;;
     70	ld8 out7=[in1]
     71	mov loc2=gp			// save global pointer
     72	mov loc4=ar.rsc			// save RSE configuration
     73	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
     74	;;
     75	ld8 gp=[in0]			// load ESI function's global pointer
     76	movl r16=PSR_BITS_TO_CLEAR
     77	mov loc3=psr			// save processor status word
     78	movl r17=PSR_BITS_TO_SET
     79	;;
     80	or loc3=loc3,r17
     81	mov b6=r2
     82	;;
     83	andcm r16=loc3,r16	// get psr with IT, DT, and RT bits cleared
     84	br.call.sptk.many rp=ia64_switch_mode_phys
     85.ret0:	mov loc5=r19			// old ar.bsp
     86	mov loc6=r20			// old sp
     87	br.call.sptk.many rp=b6		// call the ESI function
     88.ret1:	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
     89	mov r16=loc3			// save virtual mode psr
     90	mov r19=loc5			// save virtual mode bspstore
     91	mov r20=loc6			// save virtual mode sp
     92	br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
     93.ret2:	mov ar.rsc=loc4			// restore RSE configuration
     94	mov ar.pfs=loc1
     95	mov rp=loc0
     96	mov gp=loc2
     97	br.ret.sptk.many rp
     98END(esi_call_phys)
     99EXPORT_SYMBOL_GPL(esi_call_phys)