cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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clear_page.S (1990B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Copyright (C) 1999-2002 Hewlett-Packard Co
      4 *	Stephane Eranian <eranian@hpl.hp.com>
      5 *	David Mosberger-Tang <davidm@hpl.hp.com>
      6 * Copyright (C) 2002 Ken Chen <kenneth.w.chen@intel.com>
      7 *
      8 * 1/06/01 davidm	Tuned for Itanium.
      9 * 2/12/02 kchen	Tuned for both Itanium and McKinley
     10 * 3/08/02 davidm	Some more tweaking
     11 */
     12
     13#include <asm/asmmacro.h>
     14#include <asm/page.h>
     15#include <asm/export.h>
     16
     17#ifdef CONFIG_ITANIUM
     18# define L3_LINE_SIZE	64	// Itanium L3 line size
     19# define PREFETCH_LINES	9	// magic number
     20#else
     21# define L3_LINE_SIZE	128	// McKinley L3 line size
     22# define PREFETCH_LINES	12	// magic number
     23#endif
     24
     25#define saved_lc	r2
     26#define dst_fetch	r3
     27#define dst1		r8
     28#define dst2		r9
     29#define dst3		r10
     30#define dst4		r11
     31
     32#define dst_last	r31
     33
     34GLOBAL_ENTRY(clear_page)
     35	.prologue
     36	.regstk 1,0,0,0
     37	mov r16 = PAGE_SIZE/L3_LINE_SIZE-1	// main loop count, -1=repeat/until
     38	.save ar.lc, saved_lc
     39	mov saved_lc = ar.lc
     40
     41	.body
     42	mov ar.lc = (PREFETCH_LINES - 1)
     43	mov dst_fetch = in0
     44	adds dst1 = 16, in0
     45	adds dst2 = 32, in0
     46	;;
     47.fetch:	stf.spill.nta [dst_fetch] = f0, L3_LINE_SIZE
     48	adds dst3 = 48, in0		// executing this multiple times is harmless
     49	br.cloop.sptk.few .fetch
     50	;;
     51	addl dst_last = (PAGE_SIZE - PREFETCH_LINES*L3_LINE_SIZE), dst_fetch
     52	mov ar.lc = r16			// one L3 line per iteration
     53	adds dst4 = 64, in0
     54	;;
     55#ifdef CONFIG_ITANIUM
     56	// Optimized for Itanium
     571:	stf.spill.nta [dst1] = f0, 64
     58	stf.spill.nta [dst2] = f0, 64
     59	cmp.lt p8,p0=dst_fetch, dst_last
     60	;;
     61#else
     62	// Optimized for McKinley
     631:	stf.spill.nta [dst1] = f0, 64
     64	stf.spill.nta [dst2] = f0, 64
     65	stf.spill.nta [dst3] = f0, 64
     66	stf.spill.nta [dst4] = f0, 128
     67	cmp.lt p8,p0=dst_fetch, dst_last
     68	;;
     69	stf.spill.nta [dst1] = f0, 64
     70	stf.spill.nta [dst2] = f0, 64
     71#endif
     72	stf.spill.nta [dst3] = f0, 64
     73(p8)	stf.spill.nta [dst_fetch] = f0, L3_LINE_SIZE
     74	br.cloop.sptk.few 1b
     75	;;
     76	mov ar.lc = saved_lc		// restore lc
     77	br.ret.sptk.many rp
     78END(clear_page)
     79EXPORT_SYMBOL(clear_page)