cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dma_timer.c (2219B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * dma_timer.c -- Freescale ColdFire DMA Timer.
      4 *
      5 * Copyright (C) 2007, Benedikt Spranger <b.spranger@linutronix.de>
      6 * Copyright (C) 2008. Sebastian Siewior, Linutronix
      7 *
      8 */
      9
     10#include <linux/clocksource.h>
     11#include <linux/io.h>
     12
     13#include <asm/machdep.h>
     14#include <asm/coldfire.h>
     15#include <asm/mcfpit.h>
     16#include <asm/mcfsim.h>
     17
     18#define DMA_TIMER_0	(0x00)
     19#define DMA_TIMER_1	(0x40)
     20#define DMA_TIMER_2	(0x80)
     21#define DMA_TIMER_3	(0xc0)
     22
     23#define DTMR0	(MCF_IPSBAR + DMA_TIMER_0 + 0x400)
     24#define DTXMR0	(MCF_IPSBAR + DMA_TIMER_0 + 0x402)
     25#define DTER0	(MCF_IPSBAR + DMA_TIMER_0 + 0x403)
     26#define DTRR0	(MCF_IPSBAR + DMA_TIMER_0 + 0x404)
     27#define DTCR0	(MCF_IPSBAR + DMA_TIMER_0 + 0x408)
     28#define DTCN0	(MCF_IPSBAR + DMA_TIMER_0 + 0x40c)
     29
     30#define DMA_FREQ    ((MCF_CLK / 2) / 16)
     31
     32/* DTMR */
     33#define DMA_DTMR_RESTART	(1 << 3)
     34#define DMA_DTMR_CLK_DIV_1	(1 << 1)
     35#define DMA_DTMR_CLK_DIV_16	(2 << 1)
     36#define DMA_DTMR_ENABLE		(1 << 0)
     37
     38static u64 cf_dt_get_cycles(struct clocksource *cs)
     39{
     40	return __raw_readl(DTCN0);
     41}
     42
     43static struct clocksource clocksource_cf_dt = {
     44	.name		= "coldfire_dma_timer",
     45	.rating		= 200,
     46	.read		= cf_dt_get_cycles,
     47	.mask		= CLOCKSOURCE_MASK(32),
     48	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
     49};
     50
     51static int __init  init_cf_dt_clocksource(void)
     52{
     53	/*
     54	 * We setup DMA timer 0 in free run mode. This incrementing counter is
     55	 * used as a highly precious clock source. With MCF_CLOCK = 150 MHz we
     56	 * get a ~213 ns resolution and the 32bit register will overflow almost
     57	 * every 15 minutes.
     58	 */
     59	__raw_writeb(0x00, DTXMR0);
     60	__raw_writeb(0x00, DTER0);
     61	__raw_writel(0x00000000, DTRR0);
     62	__raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
     63	return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ);
     64}
     65
     66arch_initcall(init_cf_dt_clocksource);
     67
     68#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
     69#define CYC2NS_SCALE	((1000000 << CYC2NS_SCALE_FACTOR) / (DMA_FREQ / 1000))
     70
     71static unsigned long long cycles2ns(unsigned long cycl)
     72{
     73	return (unsigned long long) ((unsigned long long)cycl *
     74			CYC2NS_SCALE) >> CYC2NS_SCALE_FACTOR;
     75}
     76
     77unsigned long long sched_clock(void)
     78{
     79	unsigned long cycl = __raw_readl(DTCN0);
     80
     81	return cycles2ns(cycl);
     82}