cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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m520x.c (5974B)

      1// SPDX-License-Identifier: GPL-2.0
      2/***************************************************************************/
      3
      4/*
      5 *  m520x.c  -- platform support for ColdFire 520x based boards
      6 *
      7 *  Copyright (C) 2005,      Freescale (www.freescale.com)
      8 *  Copyright (C) 2005,      Intec Automation (mike@steroidmicros.com)
      9 *  Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
     10 *  Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
     11 */
     12
     13/***************************************************************************/
     14
     15#include <linux/clkdev.h>
     16#include <linux/kernel.h>
     17#include <linux/param.h>
     18#include <linux/init.h>
     19#include <linux/io.h>
     20#include <asm/machdep.h>
     21#include <asm/coldfire.h>
     22#include <asm/mcfsim.h>
     23#include <asm/mcfuart.h>
     24#include <asm/mcfclk.h>
     25
     26/***************************************************************************/
     27
     28DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
     29DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
     30DEFINE_CLK(0, "edma", 17, MCF_CLK);
     31DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
     32DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
     33DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
     34DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
     35DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
     36DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
     37DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
     38DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
     39DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
     40DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
     41DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
     42
     43DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
     44DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
     45DEFINE_CLK(0, "mcfeport.0", 34, MCF_CLK);
     46DEFINE_CLK(0, "mcfwdt.0", 35, MCF_CLK);
     47DEFINE_CLK(0, "pll.0", 36, MCF_CLK);
     48DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
     49DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
     50DEFINE_CLK(0, "sdram.0", 42, MCF_CLK);
     51
     52static struct clk_lookup m520x_clk_lookup[] = {
     53	CLKDEV_INIT(NULL, "flexbus", &__clk_0_2),
     54	CLKDEV_INIT("fec.0", NULL, &__clk_0_12),
     55	CLKDEV_INIT("edma", NULL, &__clk_0_17),
     56	CLKDEV_INIT("intc.0", NULL, &__clk_0_18),
     57	CLKDEV_INIT("iack.0", NULL, &__clk_0_21),
     58	CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
     59	CLKDEV_INIT("mcfqspi.0", NULL, &__clk_0_23),
     60	CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24),
     61	CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25),
     62	CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26),
     63	CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28),
     64	CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29),
     65	CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30),
     66	CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31),
     67	CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32),
     68	CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33),
     69	CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_34),
     70	CLKDEV_INIT("mcfwdt.0", NULL, &__clk_0_35),
     71	CLKDEV_INIT(NULL, "pll.0", &__clk_0_36),
     72	CLKDEV_INIT(NULL, "sys.0", &__clk_0_40),
     73	CLKDEV_INIT("gpio.0", NULL, &__clk_0_41),
     74	CLKDEV_INIT("sdram.0", NULL, &__clk_0_42),
     75};
     76
     77static struct clk * const enable_clks[] __initconst = {
     78	&__clk_0_2, /* flexbus */
     79	&__clk_0_18, /* intc.0 */
     80	&__clk_0_21, /* iack.0 */
     81	&__clk_0_24, /* mcfuart.0 */
     82	&__clk_0_25, /* mcfuart.1 */
     83	&__clk_0_26, /* mcfuart.2 */
     84
     85	&__clk_0_32, /* mcfpit.0 */
     86	&__clk_0_33, /* mcfpit.1 */
     87	&__clk_0_34, /* mcfeport.0 */
     88	&__clk_0_36, /* pll.0 */
     89	&__clk_0_40, /* sys.0 */
     90	&__clk_0_41, /* gpio.0 */
     91	&__clk_0_42, /* sdram.0 */
     92};
     93
     94static struct clk * const disable_clks[] __initconst = {
     95	&__clk_0_12, /* fec.0 */
     96	&__clk_0_17, /* edma */
     97	&__clk_0_22, /* imx1-i2c.0 */
     98	&__clk_0_23, /* mcfqspi.0 */
     99	&__clk_0_28, /* mcftmr.0 */
    100	&__clk_0_29, /* mcftmr.1 */
    101	&__clk_0_30, /* mcftmr.2 */
    102	&__clk_0_31, /* mcftmr.3 */
    103	&__clk_0_35, /* mcfwdt.0 */
    104};
    105
    106
    107static void __init m520x_clk_init(void)
    108{
    109	unsigned i;
    110
    111	/* make sure these clocks are enabled */
    112	for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
    113		__clk_init_enabled(enable_clks[i]);
    114	/* make sure these clocks are disabled */
    115	for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
    116		__clk_init_disabled(disable_clks[i]);
    117
    118	clkdev_add_table(m520x_clk_lookup, ARRAY_SIZE(m520x_clk_lookup));
    119}
    120
    121/***************************************************************************/
    122
    123static void __init m520x_qspi_init(void)
    124{
    125#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
    126	u16 par;
    127	/* setup Port QS for QSPI with gpio CS control */
    128	writeb(0x3f, MCF_GPIO_PAR_QSPI);
    129	/* make U1CTS and U2RTS gpio for cs_control */
    130	par = readw(MCF_GPIO_PAR_UART);
    131	par &= 0x00ff;
    132	writew(par, MCF_GPIO_PAR_UART);
    133#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
    134}
    135
    136/***************************************************************************/
    137
    138static void __init m520x_i2c_init(void)
    139{
    140#if IS_ENABLED(CONFIG_I2C_IMX)
    141	u8 par;
    142
    143	/* setup Port FECI2C Pin Assignment Register for I2C */
    144	/*  set PAR_SCL to SCL and PAR_SDA to SDA */
    145	par = readb(MCF_GPIO_PAR_FECI2C);
    146	par |= 0x0f;
    147	writeb(par, MCF_GPIO_PAR_FECI2C);
    148#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
    149}
    150
    151/***************************************************************************/
    152
    153static void __init m520x_uarts_init(void)
    154{
    155	u16 par;
    156	u8 par2;
    157
    158	/* UART0 and UART1 GPIO pin setup */
    159	par = readw(MCF_GPIO_PAR_UART);
    160	par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
    161	par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
    162	writew(par, MCF_GPIO_PAR_UART);
    163
    164	/* UART1 GPIO pin setup */
    165	par2 = readb(MCF_GPIO_PAR_FECI2C);
    166	par2 &= ~0x0F;
    167	par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
    168		MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
    169	writeb(par2, MCF_GPIO_PAR_FECI2C);
    170}
    171
    172/***************************************************************************/
    173
    174static void __init m520x_fec_init(void)
    175{
    176	u8 v;
    177
    178	/* Set multi-function pins to ethernet mode */
    179	v = readb(MCF_GPIO_PAR_FEC);
    180	writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
    181
    182	v = readb(MCF_GPIO_PAR_FECI2C);
    183	writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
    184}
    185
    186/***************************************************************************/
    187
    188void __init config_BSP(char *commandp, int size)
    189{
    190	mach_sched_init = hw_timer_init;
    191	m520x_clk_init();
    192	m520x_uarts_init();
    193	m520x_fec_init();
    194	m520x_qspi_init();
    195	m520x_i2c_init();
    196}
    197
    198/***************************************************************************/