cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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m5249.c (3845B)

      1// SPDX-License-Identifier: GPL-2.0
      2/***************************************************************************/
      3
      4/*
      5 *	m5249.c  -- platform support for ColdFire 5249 based boards
      6 *
      7 *	Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
      8 */
      9
     10/***************************************************************************/
     11
     12#include <linux/clkdev.h>
     13#include <linux/kernel.h>
     14#include <linux/param.h>
     15#include <linux/init.h>
     16#include <linux/io.h>
     17#include <linux/platform_device.h>
     18#include <asm/machdep.h>
     19#include <asm/coldfire.h>
     20#include <asm/mcfsim.h>
     21#include <asm/mcfclk.h>
     22
     23/***************************************************************************/
     24
     25DEFINE_CLK(pll, "pll.0", MCF_CLK);
     26DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
     27
     28struct clk_lookup m5249_clk_lookup[] = {
     29	CLKDEV_INIT(NULL, "pll.0", &clk_pll),
     30	CLKDEV_INIT(NULL, "sys.0", &clk_sys),
     31	CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
     32	CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
     33	CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
     34	CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
     35	CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
     36	CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
     37	CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys),
     38};
     39
     40/***************************************************************************/
     41
     42#ifdef CONFIG_M5249C3
     43
     44static struct resource m5249_smc91x_resources[] = {
     45	{
     46		.start		= 0xe0000300,
     47		.end		= 0xe0000300 + 0x100,
     48		.flags		= IORESOURCE_MEM,
     49	},
     50	{
     51		.start		= MCF_IRQ_GPIO6,
     52		.end		= MCF_IRQ_GPIO6,
     53		.flags		= IORESOURCE_IRQ,
     54	},
     55};
     56
     57static struct platform_device m5249_smc91x = {
     58	.name			= "smc91x",
     59	.id			= 0,
     60	.num_resources		= ARRAY_SIZE(m5249_smc91x_resources),
     61	.resource		= m5249_smc91x_resources,
     62};
     63
     64#endif /* CONFIG_M5249C3 */
     65
     66static struct platform_device *m5249_devices[] __initdata = {
     67#ifdef CONFIG_M5249C3
     68	&m5249_smc91x,
     69#endif
     70};
     71
     72/***************************************************************************/
     73
     74static void __init m5249_qspi_init(void)
     75{
     76#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
     77	/* QSPI irq setup */
     78	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
     79	       MCFSIM_QSPIICR);
     80	mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
     81#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
     82}
     83
     84/***************************************************************************/
     85
     86static void __init m5249_i2c_init(void)
     87{
     88#if IS_ENABLED(CONFIG_I2C_IMX)
     89	u32 r;
     90
     91	/* first I2C controller uses regular irq setup */
     92	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
     93	       MCFSIM_I2CICR);
     94	mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
     95
     96	/* second I2C controller is completely different */
     97	r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
     98	r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
     99	r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
    100	writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
    101#endif /* CONFIG_I2C_IMX */
    102}
    103
    104/***************************************************************************/
    105
    106#ifdef CONFIG_M5249C3
    107
    108static void __init m5249_smc91x_init(void)
    109{
    110	u32  gpio;
    111
    112	/* Set the GPIO line as interrupt source for smc91x device */
    113	gpio = readl(MCFSIM2_GPIOINTENABLE);
    114	writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
    115
    116	gpio = readl(MCFINTC2_INTPRI5);
    117	writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
    118}
    119
    120#endif /* CONFIG_M5249C3 */
    121
    122/***************************************************************************/
    123
    124void __init config_BSP(char *commandp, int size)
    125{
    126	mach_sched_init = hw_timer_init;
    127
    128#ifdef CONFIG_M5249C3
    129	m5249_smc91x_init();
    130#endif
    131	m5249_qspi_init();
    132	m5249_i2c_init();
    133
    134	clkdev_add_table(m5249_clk_lookup, ARRAY_SIZE(m5249_clk_lookup));
    135}
    136
    137/***************************************************************************/
    138
    139static int __init init_BSP(void)
    140{
    141	platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
    142	return 0;
    143}
    144
    145arch_initcall(init_BSP);
    146
    147/***************************************************************************/