m527x.c (4117B)
1// SPDX-License-Identifier: GPL-2.0 2/***************************************************************************/ 3 4/* 5 * m527x.c -- platform support for ColdFire 527x based boards 6 * 7 * Sub-architcture dependent initialization code for the Freescale 8 * 5270/5271 and 5274/5275 CPUs. 9 * 10 * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com) 11 * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) 12 */ 13 14/***************************************************************************/ 15 16#include <linux/clkdev.h> 17#include <linux/kernel.h> 18#include <linux/param.h> 19#include <linux/init.h> 20#include <linux/io.h> 21#include <asm/machdep.h> 22#include <asm/coldfire.h> 23#include <asm/mcfsim.h> 24#include <asm/mcfuart.h> 25#include <asm/mcfclk.h> 26 27/***************************************************************************/ 28 29DEFINE_CLK(pll, "pll.0", MCF_CLK); 30DEFINE_CLK(sys, "sys.0", MCF_BUSCLK); 31 32static struct clk_lookup m527x_clk_lookup[] = { 33 CLKDEV_INIT(NULL, "pll.0", &clk_pll), 34 CLKDEV_INIT(NULL, "sys.0", &clk_sys), 35 CLKDEV_INIT("mcfpit.0", NULL, &clk_pll), 36 CLKDEV_INIT("mcfpit.1", NULL, &clk_pll), 37 CLKDEV_INIT("mcfpit.2", NULL, &clk_pll), 38 CLKDEV_INIT("mcfpit.3", NULL, &clk_pll), 39 CLKDEV_INIT("mcfuart.0", NULL, &clk_sys), 40 CLKDEV_INIT("mcfuart.1", NULL, &clk_sys), 41 CLKDEV_INIT("mcfuart.2", NULL, &clk_sys), 42 CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys), 43 CLKDEV_INIT("fec.0", NULL, &clk_sys), 44 CLKDEV_INIT("fec.1", NULL, &clk_sys), 45 CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys), 46}; 47 48/***************************************************************************/ 49 50static void __init m527x_qspi_init(void) 51{ 52#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) 53#if defined(CONFIG_M5271) 54 u16 par; 55 56 /* setup QSPS pins for QSPI with gpio CS control */ 57 writeb(0x1f, MCFGPIO_PAR_QSPI); 58 /* and CS2 & CS3 as gpio */ 59 par = readw(MCFGPIO_PAR_TIMER); 60 par &= 0x3f3f; 61 writew(par, MCFGPIO_PAR_TIMER); 62#elif defined(CONFIG_M5275) 63 /* setup QSPS pins for QSPI with gpio CS control */ 64 writew(0x003e, MCFGPIO_PAR_QSPI); 65#endif 66#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */ 67} 68 69/***************************************************************************/ 70 71static void __init m527x_i2c_init(void) 72{ 73#if IS_ENABLED(CONFIG_I2C_IMX) 74#if defined(CONFIG_M5271) 75 u8 par; 76 77 /* setup Port FECI2C Pin Assignment Register for I2C */ 78 /* set PAR_SCL to SCL and PAR_SDA to SDA */ 79 par = readb(MCFGPIO_PAR_FECI2C); 80 par |= 0x0f; 81 writeb(par, MCFGPIO_PAR_FECI2C); 82#elif defined(CONFIG_M5275) 83 u16 par; 84 85 /* setup Port FECI2C Pin Assignment Register for I2C */ 86 /* set PAR_SCL to SCL and PAR_SDA to SDA */ 87 par = readw(MCFGPIO_PAR_FECI2C); 88 par |= 0x0f; 89 writew(par, MCFGPIO_PAR_FECI2C); 90#endif 91#endif /* IS_ENABLED(CONFIG_I2C_IMX) */ 92} 93 94/***************************************************************************/ 95 96static void __init m527x_uarts_init(void) 97{ 98 u16 sepmask; 99 100 /* 101 * External Pin Mask Setting & Enable External Pin for Interface 102 */ 103 sepmask = readw(MCFGPIO_PAR_UART); 104 sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK; 105 writew(sepmask, MCFGPIO_PAR_UART); 106} 107 108/***************************************************************************/ 109 110static void __init m527x_fec_init(void) 111{ 112 u8 v; 113 114 /* Set multi-function pins to ethernet mode for fec0 */ 115#if defined(CONFIG_M5271) 116 v = readb(MCFGPIO_PAR_FECI2C); 117 writeb(v | 0xf0, MCFGPIO_PAR_FECI2C); 118#else 119 u16 par; 120 121 par = readw(MCFGPIO_PAR_FECI2C); 122 writew(par | 0xf00, MCFGPIO_PAR_FECI2C); 123 v = readb(MCFGPIO_PAR_FEC0HL); 124 writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL); 125 126 /* Set multi-function pins to ethernet mode for fec1 */ 127 par = readw(MCFGPIO_PAR_FECI2C); 128 writew(par | 0xa0, MCFGPIO_PAR_FECI2C); 129 v = readb(MCFGPIO_PAR_FEC1HL); 130 writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL); 131#endif 132} 133 134/***************************************************************************/ 135 136void __init config_BSP(char *commandp, int size) 137{ 138 mach_sched_init = hw_timer_init; 139 m527x_uarts_init(); 140 m527x_fec_init(); 141 m527x_qspi_init(); 142 m527x_i2c_init(); 143 clkdev_add_table(m527x_clk_lookup, ARRAY_SIZE(m527x_clk_lookup)); 144} 145 146/***************************************************************************/