cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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m5307.c (2710B)

      1// SPDX-License-Identifier: GPL-2.0
      2/***************************************************************************/
      3
      4/*
      5 *	m5307.c  -- platform support for ColdFire 5307 based boards
      6 *
      7 *	Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
      8 *	Copyright (C) 2000, Lineo (www.lineo.com)
      9 */
     10
     11/***************************************************************************/
     12
     13#include <linux/clkdev.h>
     14#include <linux/kernel.h>
     15#include <linux/param.h>
     16#include <linux/init.h>
     17#include <linux/io.h>
     18#include <asm/machdep.h>
     19#include <asm/coldfire.h>
     20#include <asm/mcfsim.h>
     21#include <asm/mcfwdebug.h>
     22#include <asm/mcfclk.h>
     23
     24/***************************************************************************/
     25
     26/*
     27 *	Some platforms need software versions of the GPIO data registers.
     28 */
     29unsigned short ppdata;
     30unsigned char ledbank = 0xff;
     31
     32/***************************************************************************/
     33
     34DEFINE_CLK(pll, "pll.0", MCF_CLK);
     35DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
     36
     37static struct clk_lookup m5307_clk_lookup[] = {
     38	CLKDEV_INIT(NULL, "pll.0", &clk_pll),
     39	CLKDEV_INIT(NULL, "sys.0", &clk_sys),
     40	CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
     41	CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
     42	CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
     43	CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
     44	CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
     45};
     46
     47/***************************************************************************/
     48
     49static void __init m5307_i2c_init(void)
     50{
     51#if IS_ENABLED(CONFIG_I2C_IMX)
     52	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
     53	       MCFSIM_I2CICR);
     54	mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
     55#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
     56}
     57
     58/***************************************************************************/
     59
     60void __init config_BSP(char *commandp, int size)
     61{
     62#if defined(CONFIG_NETtel) || \
     63    defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
     64	/* Copy command line from FLASH to local buffer... */
     65	memcpy(commandp, (char *) 0xf0004000, size);
     66	commandp[size-1] = 0;
     67#endif
     68
     69	mach_sched_init = hw_timer_init;
     70
     71	/* Only support the external interrupts on their primary level */
     72	mcf_mapirq2imr(25, MCFINTC_EINT1);
     73	mcf_mapirq2imr(27, MCFINTC_EINT3);
     74	mcf_mapirq2imr(29, MCFINTC_EINT5);
     75	mcf_mapirq2imr(31, MCFINTC_EINT7);
     76
     77#ifdef CONFIG_BDM_DISABLE
     78	/*
     79	 * Disable the BDM clocking.  This also turns off most of the rest of
     80	 * the BDM device.  This is good for EMC reasons. This option is not
     81	 * incompatible with the memory protection option.
     82	 */
     83	wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
     84#endif
     85	m5307_i2c_init();
     86
     87	clkdev_add_table(m5307_clk_lookup, ARRAY_SIZE(m5307_clk_lookup));
     88}
     89
     90/***************************************************************************/