cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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m54xx.c (2983B)

      1// SPDX-License-Identifier: GPL-2.0
      2/***************************************************************************/
      3
      4/*
      5 *	m54xx.c  -- platform support for ColdFire 54xx based boards
      6 *
      7 *	Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
      8 */
      9
     10/***************************************************************************/
     11
     12#include <linux/clkdev.h>
     13#include <linux/kernel.h>
     14#include <linux/param.h>
     15#include <linux/init.h>
     16#include <linux/interrupt.h>
     17#include <linux/io.h>
     18#include <linux/mm.h>
     19#include <linux/clk.h>
     20#include <linux/memblock.h>
     21#include <asm/pgalloc.h>
     22#include <asm/machdep.h>
     23#include <asm/coldfire.h>
     24#include <asm/m54xxsim.h>
     25#include <asm/mcfuart.h>
     26#include <asm/mcfclk.h>
     27#include <asm/m54xxgpt.h>
     28#ifdef CONFIG_MMU
     29#include <asm/mmu_context.h>
     30#endif
     31
     32/***************************************************************************/
     33
     34DEFINE_CLK(pll, "pll.0", MCF_CLK);
     35DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
     36
     37static struct clk_lookup m54xx_clk_lookup[] = {
     38	CLKDEV_INIT(NULL, "pll.0", &clk_pll),
     39	CLKDEV_INIT(NULL, "sys.0", &clk_sys),
     40	CLKDEV_INIT("mcfslt.0", NULL, &clk_sys),
     41	CLKDEV_INIT("mcfslt.1", NULL, &clk_sys),
     42	CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
     43	CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
     44	CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
     45	CLKDEV_INIT("mcfuart.3", NULL, &clk_sys),
     46	CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
     47};
     48
     49/***************************************************************************/
     50
     51static void __init m54xx_uarts_init(void)
     52{
     53	/* enable io pins */
     54	__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
     55	__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
     56		MCFGPIO_PAR_PSC1);
     57	__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
     58		MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
     59	__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
     60}
     61
     62/***************************************************************************/
     63
     64static void __init m54xx_i2c_init(void)
     65{
     66#if IS_ENABLED(CONFIG_I2C_IMX)
     67	u32 r;
     68
     69	/* set the fec/i2c/irq pin assignment register for i2c */
     70	r = readl(MCF_PAR_FECI2CIRQ);
     71	r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL;
     72	writel(r, MCF_PAR_FECI2CIRQ);
     73#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
     74}
     75
     76/***************************************************************************/
     77
     78static void mcf54xx_reset(void)
     79{
     80	/* disable interrupts and enable the watchdog */
     81	asm("movew #0x2700, %sr\n");
     82	__raw_writel(0, MCF_GPT_GMS0);
     83	__raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
     84	__raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
     85		MCF_GPT_GMS0);
     86}
     87
     88/***************************************************************************/
     89
     90void __init config_BSP(char *commandp, int size)
     91{
     92	mach_reset = mcf54xx_reset;
     93	mach_sched_init = hw_timer_init;
     94	m54xx_uarts_init();
     95	m54xx_i2c_init();
     96
     97	clkdev_add_table(m54xx_clk_lookup, ARRAY_SIZE(m54xx_clk_lookup));
     98}
     99
    100/***************************************************************************/