cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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io_no.h (4196B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef _M68KNOMMU_IO_H
      3#define _M68KNOMMU_IO_H
      4
      5/*
      6 * Convert a physical memory address into a IO memory address.
      7 * For us this is trivially a type cast.
      8 */
      9#define iomem(a)	((void __iomem *) (a))
     10
     11/*
     12 * The non-MMU m68k and ColdFire IO and memory mapped hardware access
     13 * functions have always worked in CPU native endian. We need to define
     14 * that behavior here first before we include asm-generic/io.h.
     15 */
     16#define __raw_readb(addr) \
     17    ({ u8 __v = (*(__force volatile u8 *) (addr)); __v; })
     18#define __raw_readw(addr) \
     19    ({ u16 __v = (*(__force volatile u16 *) (addr)); __v; })
     20#define __raw_readl(addr) \
     21    ({ u32 __v = (*(__force volatile u32 *) (addr)); __v; })
     22
     23#define __raw_writeb(b, addr) (void)((*(__force volatile u8 *) (addr)) = (b))
     24#define __raw_writew(b, addr) (void)((*(__force volatile u16 *) (addr)) = (b))
     25#define __raw_writel(b, addr) (void)((*(__force volatile u32 *) (addr)) = (b))
     26
     27#if defined(CONFIG_COLDFIRE)
     28/*
     29 * For ColdFire platforms we may need to do some extra checks for what
     30 * type of address range we are accessing. Include the ColdFire platform
     31 * definitions so we can figure out if need to do something special.
     32 */
     33#include <asm/byteorder.h>
     34#include <asm/coldfire.h>
     35#include <asm/mcfsim.h>
     36#endif /* CONFIG_COLDFIRE */
     37
     38#if defined(IOMEMBASE)
     39/*
     40 * The ColdFire SoC internal peripherals are mapped into virtual address
     41 * space using the ACR registers of the cache control unit. This means we
     42 * are using a 1:1 physical:virtual mapping for them. We can quickly
     43 * determine if we are accessing an internal peripheral device given the
     44 * physical or vitrual address using the same range check. This check logic
     45 * applies just the same of there is no MMU but something like a PCI bus
     46 * is present.
     47 */
     48static int __cf_internalio(unsigned long addr)
     49{
     50	return (addr >= IOMEMBASE) && (addr <= IOMEMBASE + IOMEMSIZE - 1);
     51}
     52
     53static int cf_internalio(const volatile void __iomem *addr)
     54{
     55	return __cf_internalio((unsigned long) addr);
     56}
     57
     58/*
     59 * We need to treat built-in peripherals and bus based address ranges
     60 * differently. Local built-in peripherals (and the ColdFire SoC parts
     61 * have quite a lot of them) are always native endian - which is big
     62 * endian on m68k/ColdFire. Bus based address ranges, like the PCI bus,
     63 * are accessed little endian - so we need to byte swap those.
     64 */
     65#define readw readw
     66static inline u16 readw(const volatile void __iomem *addr)
     67{
     68	if (cf_internalio(addr))
     69		return __raw_readw(addr);
     70	return swab16(__raw_readw(addr));
     71}
     72
     73#define readl readl
     74static inline u32 readl(const volatile void __iomem *addr)
     75{
     76	if (cf_internalio(addr))
     77		return __raw_readl(addr);
     78	return swab32(__raw_readl(addr));
     79}
     80
     81#define writew writew
     82static inline void writew(u16 value, volatile void __iomem *addr)
     83{
     84	if (cf_internalio(addr))
     85		__raw_writew(value, addr);
     86	else
     87		__raw_writew(swab16(value), addr);
     88}
     89
     90#define writel writel
     91static inline void writel(u32 value, volatile void __iomem *addr)
     92{
     93	if (cf_internalio(addr))
     94		__raw_writel(value, addr);
     95	else
     96		__raw_writel(swab32(value), addr);
     97}
     98
     99#else
    100
    101#define readb __raw_readb
    102#define readw __raw_readw
    103#define readl __raw_readl
    104#define writeb __raw_writeb
    105#define writew __raw_writew
    106#define writel __raw_writel
    107
    108#endif /* IOMEMBASE */
    109
    110#if defined(CONFIG_PCI)
    111/*
    112 * Support for PCI bus access uses the asm-generic access functions.
    113 * We need to supply the base address and masks for the normal memory
    114 * and IO address space mappings.
    115 */
    116#define PCI_MEM_PA	0xf0000000		/* Host physical address */
    117#define PCI_MEM_BA	0xf0000000		/* Bus physical address */
    118#define PCI_MEM_SIZE	0x08000000		/* 128 MB */
    119#define PCI_MEM_MASK	(PCI_MEM_SIZE - 1)
    120
    121#define PCI_IO_PA	0xf8000000		/* Host physical address */
    122#define PCI_IO_BA	0x00000000		/* Bus physical address */
    123#define PCI_IO_SIZE	0x00010000		/* 64k */
    124#define PCI_IO_MASK	(PCI_IO_SIZE - 1)
    125
    126#define HAVE_ARCH_PIO_SIZE
    127#define PIO_OFFSET	0
    128#define PIO_MASK	0xffff
    129#define PIO_RESERVED	0x10000
    130#define PCI_IOBASE	((void __iomem *) PCI_IO_PA)
    131#define PCI_SPACE_LIMIT	PCI_IO_MASK
    132#endif /* CONFIG_PCI */
    133
    134#include <asm/kmap.h>
    135#include <asm/virtconvert.h>
    136
    137#endif /* _M68KNOMMU_IO_H */