m5307sim.h (7698B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/****************************************************************************/ 3 4/* 5 * m5307sim.h -- ColdFire 5307 System Integration Module support. 6 * 7 * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd. 8 * (C) Copyright 1999, Lineo (www.lineo.com) 9 * 10 * Modified by David W. Miller for the MCF5307 Eval Board. 11 */ 12 13/****************************************************************************/ 14#ifndef m5307sim_h 15#define m5307sim_h 16/****************************************************************************/ 17 18#define CPU_NAME "COLDFIRE(m5307)" 19#define CPU_INSTR_PER_JIFFY 3 20#define MCF_BUSCLK (MCF_CLK / 2) 21 22#include <asm/m53xxacr.h> 23 24/* 25 * Define the 5307 SIM register set addresses. 26 */ 27#define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */ 28#define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */ 29#define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */ 30#define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/ 31#define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */ 32#define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */ 33#define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */ 34#define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */ 35#define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */ 36#define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */ 37#define MCFSIM_AVR (MCF_MBAR + 0x4b) /* Autovector Ctrl */ 38#define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */ 39#define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */ 40#define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */ 41#define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */ 42#define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */ 43#define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */ 44#define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */ 45#define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */ 46#define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */ 47#define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */ 48#define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */ 49#define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */ 50 51#define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */ 52#define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */ 53#define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */ 54#define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */ 55#define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */ 56#define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */ 57 58#ifdef CONFIG_OLDMASK 59#define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */ 60#define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */ 61#define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */ 62#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ 63#define MCFSIM_CSMR3 (MCF_MBAR + 0xaa) /* CS 3 Mask reg */ 64#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ 65#define MCFSIM_CSMR4 (MCF_MBAR + 0xb6) /* CS 4 Mask reg */ 66#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ 67#define MCFSIM_CSMR5 (MCF_MBAR + 0xc2) /* CS 5 Mask reg */ 68#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ 69#define MCFSIM_CSMR6 (MCF_MBAR + 0xce) /* CS 6 Mask reg */ 70#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ 71#define MCFSIM_CSMR7 (MCF_MBAR + 0xda) /* CS 7 Mask reg */ 72#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ 73#else 74#define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */ 75#define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */ 76#define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */ 77#define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */ 78#define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */ 79#define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */ 80#define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */ 81#define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */ 82#define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */ 83#define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */ 84#define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */ 85#define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */ 86#define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */ 87#define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */ 88#define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */ 89#define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */ 90#define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */ 91#define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */ 92#endif /* CONFIG_OLDMASK */ 93 94#define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */ 95#define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM Addr/Ctrl 0 */ 96#define MCFSIM_DMR0 (MCF_MBAR + 0x10c) /* DRAM Mask 0 */ 97#define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM Addr/Ctrl 1 */ 98#define MCFSIM_DMR1 (MCF_MBAR + 0x114) /* DRAM Mask 1 */ 99 100/* 101 * Timer module. 102 */ 103#define MCFTIMER_BASE1 (MCF_MBAR + 0x140) /* Base of TIMER1 */ 104#define MCFTIMER_BASE2 (MCF_MBAR + 0x180) /* Base of TIMER2 */ 105 106#define MCFSIM_PADDR (MCF_MBAR + 0x244) 107#define MCFSIM_PADAT (MCF_MBAR + 0x248) 108 109/* 110 * DMA unit base addresses. 111 */ 112#define MCFDMA_BASE0 (MCF_MBAR + 0x300) /* Base address DMA 0 */ 113#define MCFDMA_BASE1 (MCF_MBAR + 0x340) /* Base address DMA 1 */ 114#define MCFDMA_BASE2 (MCF_MBAR + 0x380) /* Base address DMA 2 */ 115#define MCFDMA_BASE3 (MCF_MBAR + 0x3C0) /* Base address DMA 3 */ 116 117/* 118 * UART module. 119 */ 120#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) 121#define MCFUART_BASE0 (MCF_MBAR + 0x200) /* Base address UART0 */ 122#define MCFUART_BASE1 (MCF_MBAR + 0x1c0) /* Base address UART1 */ 123#else 124#define MCFUART_BASE0 (MCF_MBAR + 0x1c0) /* Base address UART0 */ 125#define MCFUART_BASE1 (MCF_MBAR + 0x200) /* Base address UART1 */ 126#endif 127 128/* 129 * Generic GPIO support 130 */ 131#define MCFGPIO_PIN_MAX 16 132#define MCFGPIO_IRQ_MAX -1 133#define MCFGPIO_IRQ_VECBASE -1 134 135 136/* Definition offset address for CS2-7 -- old mask 5307 */ 137 138#define MCF5307_CS2 (0x400000) 139#define MCF5307_CS3 (0x600000) 140#define MCF5307_CS4 (0x800000) 141#define MCF5307_CS5 (0xA00000) 142#define MCF5307_CS6 (0xC00000) 143#define MCF5307_CS7 (0xE00000) 144 145 146/* 147 * Some symbol defines for the above... 148 */ 149#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ 150#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ 151#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ 152#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ 153#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ 154#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ 155#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ 156#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ 157#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 158#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 159 160/* 161 * Some symbol defines for the Parallel Port Pin Assignment Register 162 */ 163#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ 164 /* Clear to select par I/O */ 165#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */ 166 /* Clear to select par I/O */ 167 168/* 169 * Defines for the IRQPAR Register 170 */ 171#define IRQ5_LEVEL4 0x80 172#define IRQ3_LEVEL6 0x40 173#define IRQ1_LEVEL2 0x20 174 175/* 176 * Define system peripheral IRQ usage. 177 */ 178#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */ 179#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */ 180#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */ 181#define MCF_IRQ_UART0 73 /* UART0 */ 182#define MCF_IRQ_UART1 74 /* UART1 */ 183 184/* 185 * I2C module 186 */ 187#define MCFI2C_BASE0 (MCF_MBAR + 0x280) 188#define MCFI2C_SIZE0 0x40 189 190/****************************************************************************/ 191#endif /* m5307sim_h */