cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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switch_to.h (1549B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef _M68K_SWITCH_TO_H
      3#define _M68K_SWITCH_TO_H
      4
      5/*
      6 * switch_to(n) should switch tasks to task ptr, first checking that
      7 * ptr isn't the current task, in which case it does nothing.  This
      8 * also clears the TS-flag if the task we switched to has used the
      9 * math co-processor latest.
     10 */
     11/*
     12 * switch_to() saves the extra registers, that are not saved
     13 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
     14 * a0-a1. Some of these are used by schedule() and its predecessors
     15 * and so we might get see unexpected behaviors when a task returns
     16 * with unexpected register values.
     17 *
     18 * syscall stores these registers itself and none of them are used
     19 * by syscall after the function in the syscall has been called.
     20 *
     21 * Beware that resume now expects *next to be in d1 and the offset of
     22 * tss to be in a1. This saves a few instructions as we no longer have
     23 * to push them onto the stack and read them back right after.
     24 *
     25 * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
     26 *
     27 * Changed 96/09/19 by Andreas Schwab
     28 * pass prev in a0, next in a1
     29 */
     30asmlinkage void resume(void);
     31#define switch_to(prev,next,last) do { \
     32  register void *_prev __asm__ ("a0") = (prev); \
     33  register void *_next __asm__ ("a1") = (next); \
     34  register void *_last __asm__ ("d1"); \
     35  __asm__ __volatile__("jbsr resume" \
     36		       : "=a" (_prev), "=a" (_next), "=d" (_last) \
     37		       : "0" (_prev), "1" (_next) \
     38		       : "d0", "d2", "d3", "d4", "d5"); \
     39  (last) = _last; \
     40} while (0)
     41
     42#endif /* _M68K_SWITCH_TO_H */