cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cpuinfo.h (2043B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Generic support for queying CPU info
      4 *
      5 * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
      6 * Copyright (C) 2007-2009 PetaLogix
      7 * Copyright (C) 2007 John Williams <jwilliams@itee.uq.edu.au>
      8 */
      9
     10#ifndef _ASM_MICROBLAZE_CPUINFO_H
     11#define _ASM_MICROBLAZE_CPUINFO_H
     12
     13#include <linux/of.h>
     14
     15/* CPU Version and FPGA Family code conversion table type */
     16struct cpu_ver_key {
     17	const char *s;
     18	const unsigned k;
     19};
     20
     21extern const struct cpu_ver_key cpu_ver_lookup[];
     22
     23struct family_string_key {
     24	const char *s;
     25	const unsigned k;
     26};
     27
     28extern const struct family_string_key family_string_lookup[];
     29
     30struct cpuinfo {
     31	/* Core CPU configuration */
     32	u32 use_instr;
     33	u32 use_mult;
     34	u32 use_fpu;
     35	u32 use_exc;
     36	u32 ver_code;
     37	u32 mmu;
     38	u32 mmu_privins;
     39	u32 endian;
     40
     41	/* CPU caches */
     42	u32 use_icache;
     43	u32 icache_tagbits;
     44	u32 icache_write;
     45	u32 icache_line_length;
     46	u32 icache_size;
     47	unsigned long icache_base;
     48	unsigned long icache_high;
     49
     50	u32 use_dcache;
     51	u32 dcache_tagbits;
     52	u32 dcache_write;
     53	u32 dcache_line_length;
     54	u32 dcache_size;
     55	u32 dcache_wb;
     56	unsigned long dcache_base;
     57	unsigned long dcache_high;
     58
     59	/* Bus connections */
     60	u32 use_dopb;
     61	u32 use_iopb;
     62	u32 use_dlmb;
     63	u32 use_ilmb;
     64	u32 num_fsl;
     65
     66	/* CPU interrupt line info */
     67	u32 irq_edge;
     68	u32 irq_positive;
     69
     70	u32 area_optimised;
     71
     72	/* HW debug support */
     73	u32 hw_debug;
     74	u32 num_pc_brk;
     75	u32 num_rd_brk;
     76	u32 num_wr_brk;
     77	u32 cpu_clock_freq; /* store real freq of cpu */
     78
     79	/* FPGA family */
     80	u32 fpga_family_code;
     81
     82	/* User define */
     83	u32 pvr_user1;
     84	u32 pvr_user2;
     85};
     86
     87extern struct cpuinfo cpuinfo;
     88
     89/* fwd declarations of the various CPUinfo populators */
     90void setup_cpuinfo(void);
     91void setup_cpuinfo_clk(void);
     92
     93void set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu);
     94void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu);
     95
     96static inline unsigned int fcpu(struct device_node *cpu, char *n)
     97{
     98	u32 val = 0;
     99
    100	of_property_read_u32(cpu, n, &val);
    101
    102	return val;
    103}
    104
    105#endif /* _ASM_MICROBLAZE_CPUINFO_H */