cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

time.c (2527B)

      1/*
      2 *  Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
      3 *
      4 *  This program is free software; you can redistribute  it and/or modify it
      5 *  under  the terms of  the GNU General  Public License as published by the
      6 *  Free Software Foundation;  either version 2 of the  License, or (at your
      7 *  option) any later version.
      8 *
      9 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
     10 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
     11 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
     12 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
     13 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     14 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
     15 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
     16 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
     17 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     18 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     19 *
     20 *  You should have received a copy of the  GNU General Public License along
     21 *  with this program; if not, write  to the Free Software Foundation, Inc.,
     22 *  675 Mass Ave, Cambridge, MA 02139, USA.
     23 */
     24
     25#include <linux/init.h>
     26#include <linux/ssb/ssb.h>
     27#include <asm/time.h>
     28#include <bcm47xx.h>
     29#include <bcm47xx_board.h>
     30
     31void __init plat_time_init(void)
     32{
     33	unsigned long hz = 0;
     34	u16 chip_id = 0;
     35	char buf[10];
     36	int len;
     37	enum bcm47xx_board board = bcm47xx_board_get();
     38
     39	/*
     40	 * Use deterministic values for initial counter interrupt
     41	 * so that calibrate delay avoids encountering a counter wrap.
     42	 */
     43	write_c0_count(0);
     44	write_c0_compare(0xffff);
     45
     46	switch (bcm47xx_bus_type) {
     47#ifdef CONFIG_BCM47XX_SSB
     48	case BCM47XX_BUS_TYPE_SSB:
     49		hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
     50		chip_id = bcm47xx_bus.ssb.chip_id;
     51		break;
     52#endif
     53#ifdef CONFIG_BCM47XX_BCMA
     54	case BCM47XX_BUS_TYPE_BCMA:
     55		hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
     56		chip_id = bcm47xx_bus.bcma.bus.chipinfo.id;
     57		break;
     58#endif
     59	}
     60
     61	if (chip_id == 0x5354) {
     62		len = bcm47xx_nvram_getenv("clkfreq", buf, sizeof(buf));
     63		if (len >= 0 && !strncmp(buf, "200", 4))
     64			hz = 100000000;
     65	}
     66
     67	switch (board) {
     68	case BCM47XX_BOARD_ASUS_WL520GC:
     69	case BCM47XX_BOARD_ASUS_WL520GU:
     70		hz = 100000000;
     71		break;
     72	default:
     73		break;
     74	}
     75
     76	if (!hz)
     77		hz = 100000000;
     78
     79	/* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
     80	mips_hpt_frequency = hz;
     81}