cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pistachio_marduk.dts (2684B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2015, 2016 Imagination Technologies Ltd.
      4 *
      5 * IMG Marduk board is also known as Creator Ci40.
      6 */
      7
      8/dts-v1/;
      9
     10#include "pistachio.dtsi"
     11
     12/ {
     13	model = "IMG Marduk (Creator Ci40)";
     14	compatible = "img,pistachio-marduk", "img,pistachio";
     15
     16	aliases {
     17		serial0 = &uart0;
     18		serial1 = &uart1;
     19		ethernet0 = &enet;
     20		spi0 = &spfi0;
     21		spi1 = &spfi1;
     22	};
     23
     24	chosen {
     25		bootargs = "root=/dev/sda1 rootwait ro lpj=723968";
     26		stdout-path = "serial1:115200";
     27	};
     28
     29	memory {
     30		device_type = "memory";
     31		reg =  <0x00000000 0x10000000>;
     32	};
     33
     34	reg_1v8: fixed-regulator {
     35		compatible = "regulator-fixed";
     36		regulator-name = "aux_adc_vref";
     37		regulator-min-microvolt = <1800000>;
     38		regulator-max-microvolt = <1800000>;
     39		regulator-boot-on;
     40	};
     41
     42	internal_dac_supply: internal-dac-supply {
     43		compatible = "regulator-fixed";
     44		regulator-name = "internal_dac_supply";
     45		regulator-min-microvolt = <1800000>;
     46		regulator-max-microvolt = <1800000>;
     47	};
     48
     49	led-controller {
     50		compatible = "pwm-leds";
     51
     52		led-1 {
     53			label = "marduk:red:heartbeat";
     54			pwms = <&pwm 3 300000>;
     55			max-brightness = <255>;
     56			linux,default-trigger = "heartbeat";
     57		};
     58	};
     59
     60	keys {
     61		compatible = "gpio-keys";
     62		button@1 {
     63			label = "Button 1";
     64			linux,code = <0x101>; /* BTN_1 */
     65			gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
     66		};
     67		button@2 {
     68			label = "Button 2";
     69			linux,code = <0x102>; /* BTN_2 */
     70			gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
     71		};
     72	};
     73};
     74
     75&internal_dac {
     76	VDD-supply = <&internal_dac_supply>;
     77};
     78
     79&spfi1 {
     80	status = "okay";
     81
     82	pinctrl-0 = <&spim1_pins>, <&spim1_quad_pins>, <&spim1_cs0_pin>,
     83		    <&spim1_cs1_pin>;
     84	pinctrl-names = "default";
     85	cs-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, <&gpio0 1 GPIO_ACTIVE_HIGH>;
     86
     87	flash@0 {
     88		compatible = "spansion,s25fl016k", "jedec,spi-nor";
     89		reg = <0>;
     90		spi-max-frequency = <50000000>;
     91	};
     92};
     93
     94&uart0 {
     95	status = "okay";
     96	assigned-clock-rates = <114278400>, <1843200>;
     97};
     98
     99&uart1 {
    100	status = "okay";
    101};
    102
    103&usb {
    104	status = "okay";
    105};
    106
    107&enet {
    108	status = "okay";
    109};
    110
    111&pin_enet {
    112	drive-strength = <2>;
    113};
    114
    115&pin_enet_phy_clk {
    116	drive-strength = <2>;
    117};
    118
    119&sdhost {
    120	status = "okay";
    121	bus-width = <4>;
    122	disable-wp;
    123};
    124
    125&pin_sdhost_cmd {
    126	drive-strength = <2>;
    127};
    128
    129&pin_sdhost_data {
    130	drive-strength = <2>;
    131};
    132
    133&pwm {
    134	status = "okay";
    135
    136	pinctrl-0 = <&pwmpdm0_pin>, <&pwmpdm1_pin>, <&pwmpdm2_pin>,
    137		    <&pwmpdm3_pin>;
    138	pinctrl-names = "default";
    139};
    140
    141&adc {
    142	status = "okay";
    143	vref-supply = <&reg_1v8>;
    144	adc-reserved-channels = <0x10>;
    145};
    146
    147&i2c2 {
    148	status = "okay";
    149	clock-frequency = <400000>;
    150
    151	tpm@20 {
    152		compatible = "infineon,slb9645tt";
    153		reg = <0x20>;
    154	};
    155
    156};
    157
    158&i2c3 {
    159	status = "okay";
    160	clock-frequency = <400000>;
    161};