cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ci20.dts (11063B)


      1// SPDX-License-Identifier: GPL-2.0
      2/dts-v1/;
      3
      4#include "jz4780.dtsi"
      5#include <dt-bindings/clock/ingenic,tcu.h>
      6#include <dt-bindings/gpio/gpio.h>
      7#include <dt-bindings/input/input.h>
      8#include <dt-bindings/interrupt-controller/irq.h>
      9#include <dt-bindings/regulator/active-semi,8865-regulator.h>
     10
     11/ {
     12	compatible = "img,ci20", "ingenic,jz4780";
     13
     14	aliases {
     15		serial0 = &uart0;
     16		serial1 = &uart1;
     17		serial3 = &uart3;
     18		serial4 = &uart4;
     19	};
     20
     21	chosen {
     22		stdout-path = &uart4;
     23	};
     24
     25	memory {
     26		device_type = "memory";
     27		reg = <0x0 0x10000000
     28		       0x30000000 0x30000000>;
     29	};
     30
     31	gpio-keys {
     32		compatible = "gpio-keys";
     33
     34		sw1 {
     35			label = "ci20:sw1";
     36			linux,code = <KEY_F13>;
     37			gpios = <&gpd 17 GPIO_ACTIVE_HIGH>;
     38			wakeup-source;
     39		};
     40	};
     41
     42	leds {
     43		compatible = "gpio-leds";
     44
     45		led0 {
     46			label = "ci20:red:led0";
     47			gpios = <&gpc 3 GPIO_ACTIVE_HIGH>;
     48			linux,default-trigger = "none";
     49		};
     50
     51		led1 {
     52			label = "ci20:red:led1";
     53			gpios = <&gpc 2 GPIO_ACTIVE_HIGH>;
     54			linux,default-trigger = "nand-disk";
     55		};
     56
     57		led2 {
     58			label = "ci20:red:led2";
     59			gpios = <&gpc 1 GPIO_ACTIVE_HIGH>;
     60			linux,default-trigger = "cpu1";
     61		};
     62
     63		led3 {
     64			label = "ci20:red:led3";
     65			gpios = <&gpc 0 GPIO_ACTIVE_HIGH>;
     66			linux,default-trigger = "cpu0";
     67		};
     68	};
     69
     70	eth0_power: fixedregulator@0 {
     71		compatible = "regulator-fixed";
     72
     73		regulator-name = "eth0_power";
     74		regulator-min-microvolt = <3300000>;
     75		regulator-max-microvolt = <3300000>;
     76
     77		gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
     78		enable-active-high;
     79	};
     80
     81	hdmi_out: connector {
     82		compatible = "hdmi-connector";
     83		label = "HDMI OUT";
     84		type = "a";
     85
     86		ddc-en-gpios = <&gpa 25 GPIO_ACTIVE_HIGH>;
     87
     88		port {
     89			hdmi_con: endpoint {
     90				remote-endpoint = <&dw_hdmi_out>;
     91			};
     92		};
     93	};
     94
     95	ir: ir {
     96		compatible = "gpio-ir-receiver";
     97		gpios = <&gpe 3 GPIO_ACTIVE_LOW>;
     98	};
     99
    100	wlan0_power: fixedregulator@1 {
    101		compatible = "regulator-fixed";
    102
    103		regulator-name = "wlan0_power";
    104
    105		gpio = <&gpb 19 GPIO_ACTIVE_LOW>;
    106		enable-active-high;
    107	};
    108
    109	otg_power: fixedregulator@2 {
    110		compatible = "regulator-fixed";
    111
    112		regulator-name = "otg_power";
    113		regulator-min-microvolt = <5000000>;
    114		regulator-max-microvolt = <5000000>;
    115
    116		gpio = <&gpf 14 GPIO_ACTIVE_LOW>;
    117		enable-active-high;
    118	};
    119};
    120
    121&ext {
    122	clock-frequency = <48000000>;
    123};
    124
    125&cgu {
    126	/*
    127	 * Use the 32.768 kHz oscillator as the parent of the RTC for a higher
    128	 * precision.
    129	 */
    130	assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
    131			  <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>,
    132			  <&cgu JZ4780_CLK_HDMI>;
    133	assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
    134				 <&cgu JZ4780_CLK_MPLL>,
    135				 <&cgu JZ4780_CLK_SSIPLL>;
    136	assigned-clock-rates = <48000000>, <0>, <54000000>, <0>, <27000000>;
    137};
    138
    139&tcu {
    140	/*
    141	 * 750 kHz for the system timers and clocksource,
    142	 * use channel #0 and #1 for the per cpu system timers,
    143	 * and use channel #2 for the clocksource.
    144	 *
    145	 * 3000 kHz for the OST timer to provide a higher
    146	 * precision clocksource.
    147	 */
    148	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
    149					  <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
    150	assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>;
    151};
    152
    153&mmc0 {
    154	status = "okay";
    155
    156	bus-width = <4>;
    157	max-frequency = <50000000>;
    158
    159	pinctrl-names = "default";
    160	pinctrl-0 = <&pins_mmc0>;
    161
    162	cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>;
    163};
    164
    165&mmc1 {
    166	status = "okay";
    167
    168	bus-width = <4>;
    169	max-frequency = <50000000>;
    170	non-removable;
    171
    172	pinctrl-names = "default";
    173	pinctrl-0 = <&pins_mmc1>;
    174
    175	brcmf: wifi@1 {
    176/*		reg = <4>;*/
    177		compatible = "brcm,bcm4330-fmac";
    178		vcc-supply = <&wlan0_power>;
    179		device-wakeup-gpios = <&gpd 9 GPIO_ACTIVE_HIGH>;
    180		shutdown-gpios = <&gpf 7 GPIO_ACTIVE_LOW>;
    181	};
    182};
    183
    184&uart0 {
    185	status = "okay";
    186
    187	pinctrl-names = "default";
    188	pinctrl-0 = <&pins_uart0>;
    189};
    190
    191&uart1 {
    192	status = "okay";
    193
    194	pinctrl-names = "default";
    195	pinctrl-0 = <&pins_uart1>;
    196};
    197
    198&uart2 {
    199	status = "okay";
    200
    201	pinctrl-names = "default";
    202	pinctrl-0 = <&pins_uart2>;
    203	uart-has-rtscts;
    204
    205	bluetooth {
    206		compatible = "brcm,bcm4330-bt";
    207		reset-gpios = <&gpf 8 GPIO_ACTIVE_HIGH>;
    208		vcc-supply = <&wlan0_power>;
    209		device-wakeup-gpios = <&gpf 5 GPIO_ACTIVE_HIGH>;
    210		host-wakeup-gpios = <&gpf 6 GPIO_ACTIVE_HIGH>;
    211		shutdown-gpios = <&gpf 4 GPIO_ACTIVE_LOW>;
    212	};
    213};
    214
    215&uart3 {
    216	status = "okay";
    217
    218	pinctrl-names = "default";
    219	pinctrl-0 = <&pins_uart3>;
    220};
    221
    222&uart4 {
    223	status = "okay";
    224
    225	pinctrl-names = "default";
    226	pinctrl-0 = <&pins_uart4>;
    227};
    228
    229&i2c0 {
    230	status = "okay";
    231
    232	pinctrl-names = "default";
    233	pinctrl-0 = <&pins_i2c0>;
    234
    235	clock-frequency = <400000>;
    236
    237	act8600: act8600@5a {
    238		compatible = "active-semi,act8600";
    239		reg = <0x5a>;
    240		status = "okay";
    241
    242		regulators {
    243			vddcore: SUDCDC1 {
    244				regulator-name = "DCDC_REG1";
    245				regulator-min-microvolt = <1100000>;
    246				regulator-max-microvolt = <1100000>;
    247				regulator-always-on;
    248			};
    249			vddmem: SUDCDC2 {
    250				regulator-name = "DCDC_REG2";
    251				regulator-min-microvolt = <1500000>;
    252				regulator-max-microvolt = <1500000>;
    253				regulator-always-on;
    254			};
    255			vcc_33: SUDCDC3 {
    256				regulator-name = "DCDC_REG3";
    257				regulator-min-microvolt = <3300000>;
    258				regulator-max-microvolt = <3300000>;
    259				regulator-always-on;
    260			};
    261			vcc_50: SUDCDC4 {
    262				regulator-name = "SUDCDC_REG4";
    263				regulator-min-microvolt = <5000000>;
    264				regulator-max-microvolt = <5000000>;
    265				regulator-always-on;
    266			};
    267			vcc_25: LDO_REG5 {
    268				regulator-name = "LDO_REG5";
    269				regulator-min-microvolt = <2500000>;
    270				regulator-max-microvolt = <2500000>;
    271				regulator-always-on;
    272			};
    273			wifi_io: LDO_REG6 {
    274				regulator-name = "LDO_REG6";
    275				regulator-min-microvolt = <2500000>;
    276				regulator-max-microvolt = <2500000>;
    277				regulator-always-on;
    278			};
    279			vcc_28: LDO_REG7 {
    280				regulator-name = "LDO_REG7";
    281				regulator-min-microvolt = <2800000>;
    282				regulator-max-microvolt = <2800000>;
    283				regulator-always-on;
    284			};
    285			vcc_15: LDO_REG8 {
    286				regulator-name = "LDO_REG8";
    287				regulator-min-microvolt = <1500000>;
    288				regulator-max-microvolt = <1500000>;
    289				regulator-always-on;
    290			};
    291			vrtc_18: LDO_REG9 {
    292				regulator-name = "LDO_REG9";
    293				/* Despite the datasheet stating 3.3V
    294				 * for REG9 and the driver expecting that,
    295				 * REG9 outputs 1.8V.
    296				 * Likely the CI20 uses a proprietary
    297				 * factory programmed chip variant.
    298				 * Since this is a simple on/off LDO the
    299				 * exact values do not matter.
    300				 */
    301				regulator-min-microvolt = <3300000>;
    302				regulator-max-microvolt = <3300000>;
    303				regulator-always-on;
    304			};
    305			vcc_11: LDO_REG10 {
    306				regulator-name = "LDO_REG10";
    307				regulator-min-microvolt = <1200000>;
    308				regulator-max-microvolt = <1200000>;
    309				regulator-always-on;
    310			};
    311		};
    312	};
    313};
    314
    315&i2c1 {
    316	status = "okay";
    317
    318	pinctrl-names = "default";
    319	pinctrl-0 = <&pins_i2c1>;
    320
    321};
    322
    323&i2c2 {
    324	status = "okay";
    325
    326	pinctrl-names = "default";
    327	pinctrl-0 = <&pins_i2c2>;
    328
    329};
    330
    331&i2c3 {
    332	status = "okay";
    333
    334	pinctrl-names = "default";
    335	pinctrl-0 = <&pins_i2c3>;
    336
    337};
    338
    339&i2c4 {
    340	status = "okay";
    341
    342	pinctrl-names = "default";
    343	pinctrl-0 = <&pins_i2c4>;
    344
    345	clock-frequency = <400000>;
    346
    347		rtc@51 {
    348			compatible = "nxp,pcf8563";
    349			reg = <0x51>;
    350
    351			interrupt-parent = <&gpf>;
    352			interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
    353		};
    354};
    355
    356&nemc {
    357	status = "okay";
    358
    359	nandc: nand-controller@1 {
    360		compatible = "ingenic,jz4780-nand";
    361		reg = <1 0 0x1000000>;
    362
    363		#address-cells = <1>;
    364		#size-cells = <0>;
    365
    366		ingenic,bch-controller = <&bch>;
    367
    368		ingenic,nemc-tAS = <10>;
    369		ingenic,nemc-tAH = <5>;
    370		ingenic,nemc-tBP = <10>;
    371		ingenic,nemc-tAW = <15>;
    372		ingenic,nemc-tSTRV = <100>;
    373
    374		/*
    375		 * Only CLE/ALE are needed for the devices that are connected, rather
    376		 * than the full address line set.
    377		 */
    378		pinctrl-names = "default";
    379		pinctrl-0 = <&pins_nemc>;
    380
    381		nand@1 {
    382			reg = <1>;
    383
    384			nand-ecc-step-size = <1024>;
    385			nand-ecc-strength = <24>;
    386			nand-ecc-mode = "hw";
    387			nand-on-flash-bbt;
    388
    389			pinctrl-names = "default";
    390			pinctrl-0 = <&pins_nemc_cs1>;
    391
    392			partitions {
    393				compatible = "fixed-partitions";
    394				#address-cells = <2>;
    395				#size-cells = <2>;
    396
    397				partition@0 {
    398					label = "u-boot-spl";
    399					reg = <0x0 0x0 0x0 0x800000>;
    400				};
    401
    402				partition@800000 {
    403					label = "u-boot";
    404					reg = <0x0 0x800000 0x0 0x200000>;
    405				};
    406
    407				partition@a00000 {
    408					label = "u-boot-env";
    409					reg = <0x0 0xa00000 0x0 0x200000>;
    410				};
    411
    412				partition@c00000 {
    413					label = "boot";
    414					reg = <0x0 0xc00000 0x0 0x4000000>;
    415				};
    416
    417				partition@4c00000 {
    418					label = "system";
    419					reg = <0x0 0x4c00000 0x1 0xfb400000>;
    420				};
    421			};
    422		};
    423	};
    424
    425	dm9000@6 {
    426		compatible = "davicom,dm9000";
    427		davicom,no-eeprom;
    428
    429		pinctrl-names = "default";
    430		pinctrl-0 = <&pins_nemc_cs6>;
    431
    432		reg = <6 0 1   /* addr */
    433		       6 2 1>; /* data */
    434
    435		ingenic,nemc-tAS = <15>;
    436		ingenic,nemc-tAH = <10>;
    437		ingenic,nemc-tBP = <20>;
    438		ingenic,nemc-tAW = <50>;
    439		ingenic,nemc-tSTRV = <100>;
    440
    441		reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
    442		vcc-supply = <&eth0_power>;
    443
    444		interrupt-parent = <&gpe>;
    445		interrupts = <19 4>;
    446
    447		nvmem-cells = <&eth0_addr>;
    448		nvmem-cell-names = "mac-address";
    449	};
    450};
    451
    452&bch {
    453	status = "okay";
    454};
    455
    456&otg_phy {
    457	status = "okay";
    458
    459	vcc-supply = <&otg_power>;
    460};
    461
    462&otg {
    463	status = "okay";
    464};
    465
    466&pinctrl {
    467	pins_uart0: uart0 {
    468		function = "uart0";
    469		groups = "uart0-data";
    470		bias-disable;
    471	};
    472
    473	pins_uart1: uart1 {
    474		function = "uart1";
    475		groups = "uart1-data";
    476		bias-disable;
    477	};
    478
    479	pins_uart2: uart2 {
    480		function = "uart2";
    481		groups = "uart2-data", "uart2-hwflow";
    482		bias-disable;
    483	};
    484
    485	pins_uart3: uart3 {
    486		function = "uart3";
    487		groups = "uart3-data", "uart3-hwflow";
    488		bias-disable;
    489	};
    490
    491	pins_uart4: uart4 {
    492		function = "uart4";
    493		groups = "uart4-data";
    494		bias-disable;
    495	};
    496
    497	pins_i2c0: i2c0 {
    498		function = "i2c0";
    499		groups = "i2c0-data";
    500		bias-disable;
    501	};
    502
    503	pins_i2c1: i2c1 {
    504		function = "i2c1";
    505		groups = "i2c1-data";
    506		bias-disable;
    507	};
    508
    509	pins_i2c2: i2c2 {
    510		function = "i2c2";
    511		groups = "i2c2-data";
    512		bias-disable;
    513	};
    514
    515	pins_i2c3: i2c3 {
    516		function = "i2c3";
    517		groups = "i2c3-data";
    518		bias-disable;
    519	};
    520
    521	pins_i2c4: i2c4 {
    522		function = "i2c4";
    523		groups = "i2c4-data-e";
    524		bias-disable;
    525	};
    526
    527	pins_hdmi_ddc: hdmi_ddc {
    528		function = "hdmi-ddc";
    529		groups = "hdmi-ddc";
    530		bias-disable;
    531	};
    532
    533	pins_nemc: nemc {
    534		function = "nemc";
    535		groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe";
    536		bias-disable;
    537	};
    538
    539	pins_nemc_cs1: nemc-cs1 {
    540		function = "nemc-cs1";
    541		groups = "nemc-cs1";
    542		bias-disable;
    543	};
    544
    545	pins_nemc_cs6: nemc-cs6 {
    546		function = "nemc-cs6";
    547		groups = "nemc-cs6";
    548		bias-disable;
    549	};
    550
    551	pins_mmc0: mmc0 {
    552		function = "mmc0";
    553		groups = "mmc0-1bit-e", "mmc0-4bit-e";
    554		bias-disable;
    555	};
    556
    557	pins_mmc1: mmc1 {
    558		function = "mmc1";
    559		groups = "mmc1-1bit-d", "mmc1-4bit-d";
    560		bias-disable;
    561	};
    562};
    563
    564&hdmi {
    565	status = "okay";
    566
    567	pinctrl-names = "default";
    568	pinctrl-0 = <&pins_hdmi_ddc>;
    569
    570	ports {
    571		#address-cells = <1>;
    572		#size-cells = <0>;
    573
    574		port@0 {
    575			reg = <0>;
    576			dw_hdmi_in: endpoint {
    577				remote-endpoint = <&lcd_out>;
    578			};
    579		};
    580
    581		port@1 {
    582			reg = <1>;
    583			dw_hdmi_out: endpoint {
    584				remote-endpoint = <&hdmi_con>;
    585			};
    586		};
    587	};
    588};
    589
    590&lcdc0 {
    591	status = "okay";
    592
    593	port {
    594		lcd_out: endpoint {
    595			remote-endpoint = <&dw_hdmi_in>;
    596		};
    597	};
    598};