cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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loongson64v_4core_virtio.dts (2501B)


      1// SPDX-License-Identifier: GPL-2.0
      2
      3#include <dt-bindings/interrupt-controller/irq.h>
      4
      5/dts-v1/;
      6/ {
      7	compatible = "loongson,loongson64v-4core-virtio";
      8	#address-cells = <2>;
      9	#size-cells = <2>;
     10
     11	cpuintc: interrupt-controller {
     12		#address-cells = <0>;
     13		#interrupt-cells = <1>;
     14		interrupt-controller;
     15		compatible = "mti,cpu-interrupt-controller";
     16	};
     17
     18	package0: bus@1fe00000 {
     19		compatible = "simple-bus";
     20		#address-cells = <2>;
     21		#size-cells = <1>;
     22		ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
     23			0 0x3ff00000 0 0x3ff00000 0x100000
     24			0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
     25
     26		liointc: interrupt-controller@3ff01400 {
     27			compatible = "loongson,liointc-1.0";
     28			reg = <0 0x3ff01400 0x64>;
     29
     30			interrupt-controller;
     31			#interrupt-cells = <2>;
     32
     33			interrupt-parent = <&cpuintc>;
     34			interrupts = <2>, <3>;
     35			interrupt-names = "int0", "int1";
     36
     37			loongson,parent_int_map = <0x00000001>, /* int0 */
     38						<0xfffffffe>, /* int1 */
     39						<0x00000000>, /* int2 */
     40						<0x00000000>; /* int3 */
     41
     42		};
     43
     44		cpu_uart0: serial@1fe001e0 {
     45			compatible = "ns16550a";
     46			reg = <0 0x1fe001e0 0x8>;
     47			clock-frequency = <33000000>;
     48			interrupt-parent = <&liointc>;
     49			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
     50			no-loopback-test;
     51		};
     52	};
     53
     54	bus@10000000 {
     55		compatible = "simple-bus";
     56		#address-cells = <2>;
     57		#size-cells = <2>;
     58		ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
     59				0 0x40000000 0 0x40000000 0 0x40000000>; /* PCI MEM */
     60
     61		rtc0: rtc@10081000 {
     62			compatible = "google,goldfish-rtc";
     63			reg = <0 0x10081000 0 0x1000>;
     64			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
     65			interrupt-parent = <&liointc>;
     66		};
     67
     68		pci@1a000000 {
     69			compatible = "pci-host-ecam-generic";
     70			device_type = "pci";
     71			#address-cells = <3>;
     72			#size-cells = <2>;
     73			#interrupt-cells = <1>;
     74
     75			bus-range = <0x0 0x1f>;
     76			reg = <0 0x1a000000 0 0x02000000>;
     77
     78			ranges = <0x01000000 0x0 0x00004000 0x0 0x18004000 0x0 0x0000c000>,
     79				 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
     80
     81			interrupt-map = <
     82				0x0000 0x0 0x0  0x1  &liointc  0x2 IRQ_TYPE_LEVEL_HIGH
     83				0x0800 0x0 0x0  0x1  &liointc  0x3 IRQ_TYPE_LEVEL_HIGH
     84				0x1000 0x0 0x0  0x1  &liointc  0x4 IRQ_TYPE_LEVEL_HIGH
     85				0x1800 0x0 0x0  0x1  &liointc  0x5 IRQ_TYPE_LEVEL_HIGH
     86				>;
     87
     88			interrupt-map-mask = <0x1800 0x0 0x0  0x7>;
     89		};
     90
     91		isa@18000000 {
     92			compatible = "isa";
     93			#address-cells = <2>;
     94			#size-cells = <1>;
     95			ranges = <1 0 0 0x18000000 0x4000>;
     96		};
     97	};
     98
     99	hypervisor {
    100		compatible = "linux,kvm";
    101	};
    102};