cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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jaguar2_pcb118.dts (1038B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Copyright (c) 2018 Microsemi Corporation
      4 */
      5
      6/dts-v1/;
      7#include "jaguar2_common.dtsi"
      8
      9/ {
     10	model = "Jaguar2/Aquantia PCB118 Reference Board";
     11	compatible = "mscc,jr2-pcb118", "mscc,jr2";
     12
     13	aliases {
     14		i2c150  = &i2c150;
     15		i2c151  = &i2c151;
     16	};
     17
     18	i2c0_imux: i2c0-imux {
     19		compatible = "i2c-mux-pinctrl";
     20		#address-cells = <1>;
     21		#size-cells = <0>;
     22		i2c-parent = <&i2c0>;
     23		pinctrl-names =
     24			"i2c150", "i2c151", "idle";
     25		pinctrl-0 = <&i2cmux_0>;
     26		pinctrl-1 = <&i2cmux_1>;
     27		pinctrl-2 = <&i2cmux_pins_i>;
     28		i2c150: i2c@0 {
     29			reg = <0>;
     30			#address-cells = <1>;
     31			#size-cells = <0>;
     32		};
     33		i2c151: i2c@1 {
     34			reg = <1>;
     35			#address-cells = <1>;
     36			#size-cells = <0>;
     37		};
     38	};
     39};
     40
     41&gpio {
     42	i2cmux_pins_i: i2cmux-pins {
     43		pins = "GPIO_17", "GPIO_16";
     44		function = "twi_scl_m";
     45		output-low;
     46	};
     47	i2cmux_0: i2cmux-0-pins {
     48		pins = "GPIO_17";
     49		function = "twi_scl_m";
     50		output-high;
     51	};
     52	i2cmux_1: i2cmux-1-pins {
     53		pins = "GPIO_16";
     54		function = "twi_scl_m";
     55		output-high;
     56	};
     57};