cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

luton.dtsi (2282B)


      1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
      2/* Copyright (c) 2020 Microsemi Corporation */
      3
      4/ {
      5	#address-cells = <1>;
      6	#size-cells = <1>;
      7	compatible = "mscc,luton";
      8
      9	cpus {
     10		#address-cells = <1>;
     11		#size-cells = <0>;
     12
     13		cpu@0 {
     14			compatible = "mips,mips24KEc";
     15			device_type = "cpu";
     16			clocks = <&cpu_clk>;
     17			reg = <0>;
     18		};
     19	};
     20
     21	aliases {
     22		serial0 = &uart0;
     23	};
     24
     25	cpuintc: interrupt-controller {
     26		#address-cells = <0>;
     27		#interrupt-cells = <1>;
     28		interrupt-controller;
     29		compatible = "mti,cpu-interrupt-controller";
     30	};
     31
     32	cpu_clk: cpu-clock {
     33		compatible = "fixed-clock";
     34		#clock-cells = <0>;
     35		clock-frequency = <416666666>;
     36	};
     37
     38	ahb_clk: ahb-clk {
     39		compatible = "fixed-factor-clock";
     40		#clock-cells = <0>;
     41		clocks = <&cpu_clk>;
     42		clock-div = <2>;
     43		clock-mult = <1>;
     44	};
     45
     46	ahb@60000000 {
     47		compatible = "simple-bus";
     48		#address-cells = <1>;
     49		#size-cells = <1>;
     50		ranges = <0 0x60000000 0x20000000>;
     51
     52		interrupt-parent = <&intc>;
     53
     54		cpu_ctrl: syscon@10000000 {
     55			compatible = "mscc,ocelot-cpu-syscon", "syscon";
     56			reg = <0x10000000 0x2c>;
     57		};
     58
     59		intc: interrupt-controller@10000084 {
     60			compatible = "mscc,luton-icpu-intr";
     61			reg = <0x10000084 0x70>;
     62			#interrupt-cells = <1>;
     63			interrupt-controller;
     64			interrupt-parent = <&cpuintc>;
     65			interrupts = <2>;
     66		};
     67
     68		uart0: serial@10100000 {
     69			pinctrl-0 = <&uart_pins>;
     70			pinctrl-names = "default";
     71			compatible = "ns16550a";
     72			reg = <0x10100000 0x20>;
     73			interrupts = <6>;
     74			clocks = <&ahb_clk>;
     75			reg-io-width = <4>;
     76			reg-shift = <2>;
     77
     78			status = "disabled";
     79		};
     80
     81		i2c0: i2c@10100400 {
     82			compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
     83			pinctrl-0 = <&i2c_pins>;
     84			pinctrl-names = "default";
     85			reg = <0x10100400 0x100>, <0x100002a4 0x8>;
     86			#address-cells = <1>;
     87			#size-cells = <0>;
     88			interrupts = <11>;
     89			clocks = <&ahb_clk>;
     90
     91			status = "disabled";
     92		};
     93
     94		gpio: pinctrl@70068 {
     95			compatible = "mscc,luton-pinctrl";
     96			reg = <0x70068 0x28>;
     97			gpio-controller;
     98			#gpio-cells = <2>;
     99			gpio-ranges = <&gpio 0 0 32>;
    100			interrupt-controller;
    101			interrupts = <13>;
    102			#interrupt-cells = <2>;
    103
    104			i2c_pins: i2c-pins {
    105				pins = "GPIO_5", "GPIO_6";
    106				function = "twi";
    107			};
    108
    109			uart_pins: uart-pins {
    110				pins = "GPIO_30", "GPIO_31";
    111				function = "uart";
    112			};
    113
    114		};
    115	};
    116};