cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

nexys4ddr.dts (2530B)

      1// SPDX-License-Identifier: GPL-2.0
      2/dts-v1/;
      3
      4#include "microAptiv.dtsi"
      5
      6/ {
      7	compatible = "digilent,nexys4ddr";
      8
      9	aliases {
     10		serial0 = &axi_uart16550;
     11	};
     12	chosen {
     13		bootargs = "console=ttyS0,115200";
     14		stdout-path = "serial0:115200n8";
     15	};
     16
     17	memory {
     18		device_type = "memory";
     19		reg = <0x0 0x08000000>;
     20	};
     21
     22	cpuintc: interrupt-controller {
     23		#address-cells = <0>;
     24		#interrupt-cells = <1>;
     25		interrupt-controller;
     26		compatible = "mti,cpu-interrupt-controller";
     27	};
     28
     29	axi_intc: interrupt-controller@10200000 {
     30		#interrupt-cells = <1>;
     31		compatible = "xlnx,xps-intc-1.00.a";
     32		interrupt-controller;
     33		reg = <0x10200000 0x10000>;
     34		xlnx,kind-of-intr = <0x0>;
     35		xlnx,num-intr-inputs = <0x6>;
     36
     37		interrupt-parent = <&cpuintc>;
     38		interrupts = <6>;
     39	};
     40
     41	axi_gpio: gpio@10600000 {
     42		#gpio-cells = <1>;
     43		compatible = "xlnx,xps-gpio-1.00.a";
     44		gpio-controller;
     45		reg = <0x10600000 0x10000>;
     46		xlnx,all-inputs = <0x0>;
     47		xlnx,dout-default = <0x0>;
     48		xlnx,gpio-width = <0x16>;
     49		xlnx,interrupt-present = <0x0>;
     50		xlnx,is-dual = <0x0>;
     51		xlnx,tri-default = <0xffffffff>;
     52	} ;
     53
     54	axi_ethernetlite: ethernet@10e00000 {
     55		compatible = "xlnx,xps-ethernetlite-3.00.a";
     56		device_type = "network";
     57		interrupt-parent = <&axi_intc>;
     58		interrupts = <1>;
     59		phy-handle = <&phy0>;
     60		reg = <0x10e00000 0x10000>;
     61		xlnx,duplex = <0x1>;
     62		xlnx,include-global-buffers = <0x1>;
     63		xlnx,include-internal-loopback = <0x0>;
     64		xlnx,include-mdio = <0x1>;
     65		xlnx,instance = "axi_ethernetlite_inst";
     66		xlnx,rx-ping-pong = <0x1>;
     67		xlnx,s-axi-id-width = <0x1>;
     68		xlnx,tx-ping-pong = <0x1>;
     69		xlnx,use-internal = <0x0>;
     70		mdio {
     71			#address-cells = <1>;
     72			#size-cells = <0>;
     73			phy0: phy@1 {
     74				device_type = "ethernet-phy";
     75				reg = <1>;
     76			};
     77		};
     78	};
     79
     80	axi_uart16550: serial@10400000 {
     81		compatible = "ns16550a";
     82		reg = <0x10400000 0x10000>;
     83
     84		reg-shift = <2>;
     85		reg-offset = <0x1000>;
     86
     87		clocks	= <&ext>;
     88
     89		interrupt-parent = <&axi_intc>;
     90		interrupts = <0>;
     91	};
     92
     93	axi_i2c: i2c@10a00000 {
     94	    compatible = "xlnx,xps-iic-2.00.a";
     95	    interrupt-parent = <&axi_intc>;
     96	    interrupts = <4>;
     97	    reg = < 0x10a00000 0x10000 >;
     98	    clocks = <&ext>;
     99	    xlnx,clk-freq = <0x5f5e100>;
    100	    xlnx,family = "Artix7";
    101	    xlnx,gpo-width = <0x1>;
    102	    xlnx,iic-freq = <0x186a0>;
    103	    xlnx,scl-inertial-delay = <0x0>;
    104	    xlnx,sda-inertial-delay = <0x0>;
    105	    xlnx,ten-bit-adr = <0x0>;
    106	    #address-cells = <1>;
    107	    #size-cells = <0>;
    108
    109	    ad7420@4b {
    110		compatible = "adi,adt7420";
    111		reg = <0x4b>;
    112	    };
    113	} ;
    114};
    115
    116&ext {
    117	clock-frequency = <50000000>;
    118};