cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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Kconfig (2284B)

      1# SPDX-License-Identifier: GPL-2.0
      2if CPU_CAVIUM_OCTEON
      3
      4config CAVIUM_CN63XXP1
      5	bool "Enable CN63XXP1 errata workarounds"
      6	default "n"
      7	help
      8	  The CN63XXP1 chip requires build time workarounds to
      9	  function reliably, select this option to enable them.  These
     10	  workarounds will cause a slight decrease in performance on
     11	  non-CN63XXP1 hardware, so it is recommended to select "n"
     12	  unless it is known the workarounds are needed.
     13
     14config CAVIUM_OCTEON_CVMSEG_SIZE
     15	int "Number of L1 cache lines reserved for CVMSEG memory"
     16	range 0 54
     17	default 1
     18	help
     19	  CVMSEG LM is a segment that accesses portions of the dcache as a
     20	  local memory; the larger CVMSEG is, the smaller the cache is.
     21	  This selects the size of CVMSEG LM, which is in cache blocks. The
     22	  legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
     23	  between zero and 6192 bytes).
     24
     25endif # CPU_CAVIUM_OCTEON
     26
     27if CAVIUM_OCTEON_SOC
     28
     29config CAVIUM_OCTEON_LOCK_L2
     30	bool "Lock often used kernel code in the L2"
     31	default "y"
     32	help
     33	  Enable locking parts of the kernel into the L2 cache.
     34
     35config CAVIUM_OCTEON_LOCK_L2_TLB
     36	bool "Lock the TLB handler in L2"
     37	depends on CAVIUM_OCTEON_LOCK_L2
     38	default "y"
     39	help
     40	  Lock the low level TLB fast path into L2.
     41
     42config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
     43	bool "Lock the exception handler in L2"
     44	depends on CAVIUM_OCTEON_LOCK_L2
     45	default "y"
     46	help
     47	  Lock the low level exception handler into L2.
     48
     49config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
     50	bool "Lock the interrupt handler in L2"
     51	depends on CAVIUM_OCTEON_LOCK_L2
     52	default "y"
     53	help
     54	  Lock the low level interrupt handler into L2.
     55
     56config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
     57	bool "Lock the 2nd level interrupt handler in L2"
     58	depends on CAVIUM_OCTEON_LOCK_L2
     59	default "y"
     60	help
     61	  Lock the 2nd level interrupt handler in L2.
     62
     63config CAVIUM_OCTEON_LOCK_L2_MEMCPY
     64	bool "Lock memcpy() in L2"
     65	depends on CAVIUM_OCTEON_LOCK_L2
     66	default "y"
     67	help
     68	  Lock the kernel's implementation of memcpy() into L2.
     69
     70config OCTEON_ILM
     71	tristate "Module to measure interrupt latency using Octeon CIU Timer"
     72	help
     73	  This driver is a module to measure interrupt latency using the
     74	  the CIU Timers on Octeon.
     75
     76	  To compile this driver as a module, choose M here.  The module
     77	  will be called octeon-ilm
     78
     79endif # CAVIUM_OCTEON_SOC