cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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irq.c (1295B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright (C) 2016 Imagination Technologies
      4 * Author: Paul Burton <paul.burton@mips.com>
      5 */
      6
      7#include <linux/clk.h>
      8#include <linux/clk-provider.h>
      9#include <linux/clocksource.h>
     10#include <linux/init.h>
     11#include <linux/types.h>
     12
     13#include <asm/irq.h>
     14#include <asm/mips-cps.h>
     15#include <asm/time.h>
     16
     17int get_c0_fdc_int(void)
     18{
     19	int mips_cpu_fdc_irq;
     20
     21	if (mips_gic_present())
     22		mips_cpu_fdc_irq = gic_get_c0_fdc_int();
     23	else if (cpu_has_veic)
     24		panic("Unimplemented!");
     25	else if (cp0_fdc_irq >= 0)
     26		mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
     27	else
     28		mips_cpu_fdc_irq = -1;
     29
     30	return mips_cpu_fdc_irq;
     31}
     32
     33int get_c0_perfcount_int(void)
     34{
     35	int mips_cpu_perf_irq;
     36
     37	if (mips_gic_present())
     38		mips_cpu_perf_irq = gic_get_c0_perfcount_int();
     39	else if (cpu_has_veic)
     40		panic("Unimplemented!");
     41	else if (cp0_perfcount_irq >= 0)
     42		mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
     43	else
     44		mips_cpu_perf_irq = -1;
     45
     46	return mips_cpu_perf_irq;
     47}
     48
     49unsigned int get_c0_compare_int(void)
     50{
     51	int mips_cpu_timer_irq;
     52
     53	if (mips_gic_present())
     54		mips_cpu_timer_irq = gic_get_c0_compare_int();
     55	else if (cpu_has_veic)
     56		panic("Unimplemented!");
     57	else
     58		mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
     59
     60	return mips_cpu_timer_irq;
     61}