cpu.h (16796B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * cpu.h: Values of the PRId register used to match up 4 * various MIPS cpu types. 5 * 6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 7 * Copyright (C) 2004, 2013 Maciej W. Rozycki 8 */ 9#ifndef _ASM_CPU_H 10#define _ASM_CPU_H 11 12#include <linux/bits.h> 13 14/* 15 As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0 16 register 15, select 0) is defined in this (backwards compatible) way: 17 18 +----------------+----------------+----------------+----------------+ 19 | Company Options| Company ID | Processor ID | Revision | 20 +----------------+----------------+----------------+----------------+ 21 31 24 23 16 15 8 7 22 23 I don't have docs for all the previous processors, but my impression is 24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 25 spec. 26*/ 27 28#define PRID_OPT_MASK 0xff000000 29 30/* 31 * Assigned Company values for bits 23:16 of the PRId register. 32 */ 33 34#define PRID_COMP_MASK 0xff0000 35 36#define PRID_COMP_LEGACY 0x000000 37#define PRID_COMP_MIPS 0x010000 38#define PRID_COMP_BROADCOM 0x020000 39#define PRID_COMP_ALCHEMY 0x030000 40#define PRID_COMP_SIBYTE 0x040000 41#define PRID_COMP_SANDCRAFT 0x050000 42#define PRID_COMP_NXP 0x060000 43#define PRID_COMP_TOSHIBA 0x070000 44#define PRID_COMP_LSI 0x080000 45#define PRID_COMP_LEXRA 0x0b0000 46#define PRID_COMP_NETLOGIC 0x0c0000 47#define PRID_COMP_CAVIUM 0x0d0000 48#define PRID_COMP_LOONGSON 0x140000 49#define PRID_COMP_INGENIC_13 0x130000 /* X2000, X2100 */ 50#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4730, JZ4740, JZ4750, JZ4755, JZ4760, X1830 */ 51#define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775, X1000 */ 52#define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */ 53 54/* 55 * Assigned Processor ID (implementation) values for bits 15:8 of the PRId 56 * register. In order to detect a certain CPU type exactly eventually 57 * additional registers may need to be examined. 58 */ 59 60#define PRID_IMP_MASK 0xff00 61 62/* 63 * These are valid when 23:16 == PRID_COMP_LEGACY 64 */ 65 66#define PRID_IMP_R2000 0x0100 67#define PRID_IMP_AU1_REV1 0x0100 68#define PRID_IMP_AU1_REV2 0x0200 69#define PRID_IMP_R3000 0x0200 /* Same as R2000A */ 70#define PRID_IMP_R6000 0x0300 /* Same as R3000A */ 71#define PRID_IMP_R4000 0x0400 72#define PRID_IMP_R6000A 0x0600 73#define PRID_IMP_R10000 0x0900 74#define PRID_IMP_R4300 0x0b00 75#define PRID_IMP_VR41XX 0x0c00 76#define PRID_IMP_R12000 0x0e00 77#define PRID_IMP_R14000 0x0f00 /* R14K && R16K */ 78#define PRID_IMP_R8000 0x1000 79#define PRID_IMP_PR4450 0x1200 80#define PRID_IMP_R4600 0x2000 81#define PRID_IMP_R4700 0x2100 82#define PRID_IMP_TX39 0x2200 83#define PRID_IMP_R4640 0x2200 84#define PRID_IMP_R4650 0x2200 /* Same as R4640 */ 85#define PRID_IMP_R5000 0x2300 86#define PRID_IMP_TX49 0x2d00 87#define PRID_IMP_SONIC 0x2400 88#define PRID_IMP_MAGIC 0x2500 89#define PRID_IMP_RM7000 0x2700 90#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ 91#define PRID_IMP_RM9000 0x3400 92#define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */ 93#define PRID_IMP_R5432 0x5400 94#define PRID_IMP_R5500 0x5500 95#define PRID_IMP_LOONGSON_64R 0x6100 /* Reduced Loongson-2 */ 96#define PRID_IMP_LOONGSON_64C 0x6300 /* Classic Loongson-2 and Loongson-3 */ 97#define PRID_IMP_LOONGSON_64G 0xc000 /* Generic Loongson-2 and Loongson-3 */ 98 99#define PRID_IMP_UNKNOWN 0xff00 100 101/* 102 * These are the PRID's for when 23:16 == PRID_COMP_MIPS 103 */ 104 105#define PRID_IMP_QEMU_GENERIC 0x0000 106#define PRID_IMP_4KC 0x8000 107#define PRID_IMP_5KC 0x8100 108#define PRID_IMP_20KC 0x8200 109#define PRID_IMP_4KEC 0x8400 110#define PRID_IMP_4KSC 0x8600 111#define PRID_IMP_25KF 0x8800 112#define PRID_IMP_5KE 0x8900 113#define PRID_IMP_4KECR2 0x9000 114#define PRID_IMP_4KEMPR2 0x9100 115#define PRID_IMP_4KSD 0x9200 116#define PRID_IMP_24K 0x9300 117#define PRID_IMP_34K 0x9500 118#define PRID_IMP_24KE 0x9600 119#define PRID_IMP_74K 0x9700 120#define PRID_IMP_1004K 0x9900 121#define PRID_IMP_1074K 0x9a00 122#define PRID_IMP_M14KC 0x9c00 123#define PRID_IMP_M14KEC 0x9e00 124#define PRID_IMP_INTERAPTIV_UP 0xa000 125#define PRID_IMP_INTERAPTIV_MP 0xa100 126#define PRID_IMP_PROAPTIV_UP 0xa200 127#define PRID_IMP_PROAPTIV_MP 0xa300 128#define PRID_IMP_P6600 0xa400 129#define PRID_IMP_M5150 0xa700 130#define PRID_IMP_P5600 0xa800 131#define PRID_IMP_I6400 0xa900 132#define PRID_IMP_M6250 0xab00 133#define PRID_IMP_I6500 0xb000 134 135/* 136 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 137 */ 138 139#define PRID_IMP_SB1 0x0100 140#define PRID_IMP_SB1A 0x1100 141 142/* 143 * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT 144 */ 145 146#define PRID_IMP_SR71000 0x0400 147 148/* 149 * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM 150 */ 151 152#define PRID_IMP_BMIPS32_REV4 0x4000 153#define PRID_IMP_BMIPS32_REV8 0x8000 154#define PRID_IMP_BMIPS3300 0x9000 155#define PRID_IMP_BMIPS3300_ALT 0x9100 156#define PRID_IMP_BMIPS3300_BUG 0x0000 157#define PRID_IMP_BMIPS43XX 0xa000 158#define PRID_IMP_BMIPS5000 0x5a00 159#define PRID_IMP_BMIPS5200 0x5b00 160 161#define PRID_REV_BMIPS4380_LO 0x0040 162#define PRID_REV_BMIPS4380_HI 0x006f 163 164/* 165 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM 166 */ 167 168#define PRID_IMP_CAVIUM_CN38XX 0x0000 169#define PRID_IMP_CAVIUM_CN31XX 0x0100 170#define PRID_IMP_CAVIUM_CN30XX 0x0200 171#define PRID_IMP_CAVIUM_CN58XX 0x0300 172#define PRID_IMP_CAVIUM_CN56XX 0x0400 173#define PRID_IMP_CAVIUM_CN50XX 0x0600 174#define PRID_IMP_CAVIUM_CN52XX 0x0700 175#define PRID_IMP_CAVIUM_CN63XX 0x9000 176#define PRID_IMP_CAVIUM_CN68XX 0x9100 177#define PRID_IMP_CAVIUM_CN66XX 0x9200 178#define PRID_IMP_CAVIUM_CN61XX 0x9300 179#define PRID_IMP_CAVIUM_CNF71XX 0x9400 180#define PRID_IMP_CAVIUM_CN78XX 0x9500 181#define PRID_IMP_CAVIUM_CN70XX 0x9600 182#define PRID_IMP_CAVIUM_CN73XX 0x9700 183#define PRID_IMP_CAVIUM_CNF75XX 0x9800 184 185/* 186 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_* 187 */ 188 189#define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */ 190#define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD ISA */ 191#define PRID_IMP_XBURST2 0x2000 /* XBurst®2 with MXU2.1 SIMD ISA */ 192 193/* 194 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC 195 */ 196#define PRID_IMP_NETLOGIC_XLR732 0x0000 197#define PRID_IMP_NETLOGIC_XLR716 0x0200 198#define PRID_IMP_NETLOGIC_XLR532 0x0900 199#define PRID_IMP_NETLOGIC_XLR308 0x0600 200#define PRID_IMP_NETLOGIC_XLR532C 0x0800 201#define PRID_IMP_NETLOGIC_XLR516C 0x0a00 202#define PRID_IMP_NETLOGIC_XLR508C 0x0b00 203#define PRID_IMP_NETLOGIC_XLR308C 0x0f00 204#define PRID_IMP_NETLOGIC_XLS608 0x8000 205#define PRID_IMP_NETLOGIC_XLS408 0x8800 206#define PRID_IMP_NETLOGIC_XLS404 0x8c00 207#define PRID_IMP_NETLOGIC_XLS208 0x8e00 208#define PRID_IMP_NETLOGIC_XLS204 0x8f00 209#define PRID_IMP_NETLOGIC_XLS108 0xce00 210#define PRID_IMP_NETLOGIC_XLS104 0xcf00 211#define PRID_IMP_NETLOGIC_XLS616B 0x4000 212#define PRID_IMP_NETLOGIC_XLS608B 0x4a00 213#define PRID_IMP_NETLOGIC_XLS416B 0x4400 214#define PRID_IMP_NETLOGIC_XLS412B 0x4c00 215#define PRID_IMP_NETLOGIC_XLS408B 0x4e00 216#define PRID_IMP_NETLOGIC_XLS404B 0x4f00 217#define PRID_IMP_NETLOGIC_AU13XX 0x8000 218 219#define PRID_IMP_NETLOGIC_XLP8XX 0x1000 220#define PRID_IMP_NETLOGIC_XLP3XX 0x1100 221#define PRID_IMP_NETLOGIC_XLP2XX 0x1200 222#define PRID_IMP_NETLOGIC_XLP9XX 0x1500 223#define PRID_IMP_NETLOGIC_XLP5XX 0x1300 224 225/* 226 * Particular Revision values for bits 7:0 of the PRId register. 227 */ 228 229#define PRID_REV_MASK 0x00ff 230 231/* 232 * Definitions for 7:0 on legacy processors 233 */ 234 235#define PRID_REV_TX4927 0x0022 236#define PRID_REV_TX4937 0x0030 237#define PRID_REV_R4400 0x0040 238#define PRID_REV_R3000A 0x0030 239#define PRID_REV_R3000 0x0020 240#define PRID_REV_R2000A 0x0010 241#define PRID_REV_TX3912 0x0010 242#define PRID_REV_TX3922 0x0030 243#define PRID_REV_TX3927 0x0040 244#define PRID_REV_VR4111 0x0050 245#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ 246#define PRID_REV_VR4121 0x0060 247#define PRID_REV_VR4122 0x0070 248#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 249#define PRID_REV_VR4130 0x0080 250#define PRID_REV_34K_V1_0_2 0x0022 251#define PRID_REV_LOONGSON1B 0x0020 252#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */ 253#define PRID_REV_LOONGSON2E 0x0002 254#define PRID_REV_LOONGSON2F 0x0003 255#define PRID_REV_LOONGSON2K_R1_0 0x0000 256#define PRID_REV_LOONGSON2K_R1_1 0x0001 257#define PRID_REV_LOONGSON2K_R1_2 0x0002 258#define PRID_REV_LOONGSON2K_R1_3 0x0003 259#define PRID_REV_LOONGSON3A_R1 0x0005 260#define PRID_REV_LOONGSON3B_R1 0x0006 261#define PRID_REV_LOONGSON3B_R2 0x0007 262#define PRID_REV_LOONGSON3A_R2_0 0x0008 263#define PRID_REV_LOONGSON3A_R3_0 0x0009 264#define PRID_REV_LOONGSON3A_R2_1 0x000c 265#define PRID_REV_LOONGSON3A_R3_1 0x000d 266 267/* 268 * Older processors used to encode processor version and revision in two 269 * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores 270 * have switched to use the 8-bits as 3:3:2 bitfield with the last field as 271 * the patch number. *ARGH* 272 */ 273#define PRID_REV_ENCODE_44(ver, rev) \ 274 ((ver) << 4 | (rev)) 275#define PRID_REV_ENCODE_332(ver, rev, patch) \ 276 ((ver) << 5 | (rev) << 2 | (patch)) 277 278/* 279 * FPU implementation/revision register (CP1 control register 0). 280 * 281 * +---------------------------------+----------------+----------------+ 282 * | 0 | Implementation | Revision | 283 * +---------------------------------+----------------+----------------+ 284 * 31 16 15 8 7 0 285 */ 286 287#define FPIR_IMP_MASK 0xff00 288 289#define FPIR_IMP_NONE 0x0000 290 291#if !defined(__ASSEMBLY__) 292 293enum cpu_type_enum { 294 CPU_UNKNOWN, 295 296 /* 297 * R2000 class processors 298 */ 299 CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, 300 CPU_R3081, CPU_R3081E, 301 302 /* 303 * R4000 class processors 304 */ 305 CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310, 306 CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650, 307 CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R10000, 308 CPU_R12000, CPU_R14000, CPU_R16000, CPU_VR41XX, CPU_VR4111, CPU_VR4121, 309 CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000, 310 CPU_SR71000, CPU_TX49XX, 311 312 /* 313 * MIPS32 class processors 314 */ 315 CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, 316 CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, 317 CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON32, CPU_M14KC, 318 CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K, 319 CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250, 320 321 /* 322 * MIPS64 class processors 323 */ 324 CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2EF, 325 CPU_LOONGSON64, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, 326 CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_I6500, 327 328 CPU_QEMU_GENERIC, 329 330 CPU_LAST 331}; 332 333#endif /* !__ASSEMBLY */ 334 335/* 336 * ISA Level encodings 337 * 338 */ 339#define MIPS_CPU_ISA_II 0x00000001 340#define MIPS_CPU_ISA_III 0x00000002 341#define MIPS_CPU_ISA_IV 0x00000004 342#define MIPS_CPU_ISA_V 0x00000008 343#define MIPS_CPU_ISA_M32R1 0x00000010 344#define MIPS_CPU_ISA_M32R2 0x00000020 345#define MIPS_CPU_ISA_M64R1 0x00000040 346#define MIPS_CPU_ISA_M64R2 0x00000080 347#define MIPS_CPU_ISA_M32R5 0x00000100 348#define MIPS_CPU_ISA_M64R5 0x00000200 349#define MIPS_CPU_ISA_M32R6 0x00000400 350#define MIPS_CPU_ISA_M64R6 0x00000800 351 352#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \ 353 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M32R6) 354#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ 355 MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \ 356 MIPS_CPU_ISA_M64R5 | MIPS_CPU_ISA_M64R6) 357 358/* 359 * CPU Option encodings 360 */ 361#define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */ 362#define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */ 363#define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */ 364#define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */ 365#define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */ 366#define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */ 367#define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */ 368#define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */ 369#define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */ 370#define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */ 371#define MIPS_CPU_CACHE_CDEX_P BIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */ 372#define MIPS_CPU_CACHE_CDEX_S BIT_ULL(12) /* ... same for seconary cache ... */ 373#define MIPS_CPU_MCHECK BIT_ULL(13) /* Machine check exception */ 374#define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */ 375#define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */ 376#define MIPS_CPU_LLSC BIT_ULL(16) /* CPU has ll/sc instructions */ 377#define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17) /* P-cache subset enforced */ 378#define MIPS_CPU_PREFETCH BIT_ULL(18) /* CPU has usable prefetch */ 379#define MIPS_CPU_VINT BIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */ 380#define MIPS_CPU_VEIC BIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */ 381#define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */ 382#define MIPS_CPU_PCI BIT_ULL(22) /* CPU has Perf Ctr Int indicator */ 383#define MIPS_CPU_RIXI BIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */ 384#define MIPS_CPU_MICROMIPS BIT_ULL(24) /* CPU has microMIPS capability */ 385#define MIPS_CPU_TLBINV BIT_ULL(25) /* CPU supports TLBINV/F */ 386#define MIPS_CPU_SEGMENTS BIT_ULL(26) /* CPU supports Segmentation Control registers */ 387#define MIPS_CPU_EVA BIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */ 388#define MIPS_CPU_HTW BIT_ULL(28) /* CPU support Hardware Page Table Walker */ 389#define MIPS_CPU_RIXIEX BIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */ 390#define MIPS_CPU_MAAR BIT_ULL(30) /* MAAR(I) registers are present */ 391#define MIPS_CPU_FRE BIT_ULL(31) /* FRE & UFE bits implemented */ 392#define MIPS_CPU_RW_LLB BIT_ULL(32) /* LLADDR/LLB writes are allowed */ 393#define MIPS_CPU_LPA BIT_ULL(33) /* CPU supports Large Physical Addressing */ 394#define MIPS_CPU_CDMM BIT_ULL(34) /* CPU has Common Device Memory Map */ 395#define MIPS_CPU_SP BIT_ULL(36) /* Small (1KB) page support */ 396#define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */ 397#define MIPS_CPU_NAN_LEGACY BIT_ULL(38) /* Legacy NaN implemented */ 398#define MIPS_CPU_NAN_2008 BIT_ULL(39) /* 2008 NaN implemented */ 399#define MIPS_CPU_VP BIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */ 400#define MIPS_CPU_LDPTE BIT_ULL(41) /* CPU has ldpte/lddir instructions */ 401#define MIPS_CPU_MVH BIT_ULL(42) /* CPU supports MFHC0/MTHC0 */ 402#define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */ 403#define MIPS_CPU_BADINSTR BIT_ULL(44) /* CPU has BadInstr register */ 404#define MIPS_CPU_BADINSTRP BIT_ULL(45) /* CPU has BadInstrP register */ 405#define MIPS_CPU_CTXTC BIT_ULL(46) /* CPU has [X]ConfigContext registers */ 406#define MIPS_CPU_PERF BIT_ULL(47) /* CPU has MIPS performance counters */ 407#define MIPS_CPU_GUESTCTL0EXT BIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */ 408#define MIPS_CPU_GUESTCTL1 BIT_ULL(49) /* CPU has VZ GuestCtl1 register */ 409#define MIPS_CPU_GUESTCTL2 BIT_ULL(50) /* CPU has VZ GuestCtl2 register */ 410#define MIPS_CPU_GUESTID BIT_ULL(51) /* CPU uses VZ ASE GuestID feature */ 411#define MIPS_CPU_DRG BIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */ 412#define MIPS_CPU_UFR BIT_ULL(53) /* CPU supports User mode FR switching */ 413#define MIPS_CPU_SHARED_FTLB_RAM \ 414 BIT_ULL(54) /* CPU shares FTLB RAM with another */ 415#define MIPS_CPU_SHARED_FTLB_ENTRIES \ 416 BIT_ULL(55) /* CPU shares FTLB entries with another */ 417#define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \ 418 BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */ 419#define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */ 420#define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */ 421#define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */ 422#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */ 423#define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */ 424#define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */ 425 426/* 427 * CPU ASE encodings 428 */ 429#define MIPS_ASE_MIPS16 0x00000001 /* code compression */ 430#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ 431#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ 432#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ 433#define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ 434#define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */ 435#define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */ 436#define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */ 437#define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */ 438#define MIPS_ASE_DSP3 0x00000200 /* Signal Processing ASE Rev 3*/ 439#define MIPS_ASE_MIPS16E2 0x00000400 /* MIPS16e2 */ 440#define MIPS_ASE_LOONGSON_MMI 0x00000800 /* Loongson MultiMedia extensions Instructions */ 441#define MIPS_ASE_LOONGSON_CAM 0x00001000 /* Loongson CAM */ 442#define MIPS_ASE_LOONGSON_EXT 0x00002000 /* Loongson EXTensions */ 443#define MIPS_ASE_LOONGSON_EXT2 0x00004000 /* Loongson EXTensions R2 */ 444 445#endif /* _ASM_CPU_H */