cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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kn02ca.h (2869B)


      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 *	include/asm-mips/dec/kn02ca.h
      4 *
      5 *	Personal DECstation 5000/xx (Maxine or KN02-CA) definitions.
      6 *
      7 *	Copyright (C) 2002, 2003  Maciej W. Rozycki
      8 */
      9#ifndef __ASM_MIPS_DEC_KN02CA_H
     10#define __ASM_MIPS_DEC_KN02CA_H
     11
     12#include <asm/dec/kn02xa.h>		/* For common definitions. */
     13
     14/*
     15 * CPU interrupt bits.
     16 */
     17#define KN02CA_CPU_INR_HALT	6	/* HALT from ACCESS.Bus */
     18#define KN02CA_CPU_INR_CASCADE	5	/* I/O ASIC cascade */
     19#define KN02CA_CPU_INR_BUS	4	/* memory, I/O bus read/write errors */
     20#define KN02CA_CPU_INR_RTC	3	/* DS1287 RTC */
     21#define KN02CA_CPU_INR_TIMER	2	/* ARC periodic timer */
     22
     23/*
     24 * I/O ASIC interrupt bits.  Star marks denote non-IRQ status bits.
     25 */
     26#define KN02CA_IO_INR_FLOPPY	15	/* 82077 FDC */
     27#define KN02CA_IO_INR_NVRAM	14	/* (*) NVRAM clear jumper */
     28#define KN02CA_IO_INR_POWERON	13	/* (*) ACCESS.Bus/power-on reset */
     29#define KN02CA_IO_INR_TC0	12	/* TURBOchannel slot #0 */
     30#define KN02CA_IO_INR_TIMER	12	/* ARC periodic timer (?) */
     31#define KN02CA_IO_INR_ISDN	11	/* Am79C30A ISDN */
     32#define KN02CA_IO_INR_NRMOD	10	/* (*) NRMOD manufacturing jumper */
     33#define KN02CA_IO_INR_ASC	9	/* ASC (NCR53C94) SCSI */
     34#define KN02CA_IO_INR_LANCE	8	/* LANCE (Am7990) Ethernet */
     35#define KN02CA_IO_INR_HDFLOPPY	7	/* (*) HD (1.44MB) floppy status */
     36#define KN02CA_IO_INR_SCC0	6	/* SCC (Z85C30) serial #0 */
     37#define KN02CA_IO_INR_TC1	5	/* TURBOchannel slot #1 */
     38#define KN02CA_IO_INR_XDFLOPPY	4	/* (*) XD (2.88MB) floppy status */
     39#define KN02CA_IO_INR_VIDEO	3	/* framebuffer */
     40#define KN02CA_IO_INR_XVIDEO	2	/* ~framebuffer */
     41#define KN02CA_IO_INR_AB_XMIT	1	/* ACCESS.bus transmit */
     42#define KN02CA_IO_INR_AB_RECV	0	/* ACCESS.bus receive */
     43
     44
     45/*
     46 * Memory Error Register bits.
     47 */
     48#define KN02CA_MER_INTR		(1<<27)		/* ARC IRQ status & ack */
     49
     50/*
     51 * Memory Size Register bits.
     52 */
     53#define KN02CA_MSR_INTREN	(1<<26)		/* ARC periodic IRQ enable */
     54#define KN02CA_MSR_MS10EN	(1<<25)		/* 10/1ms IRQ period select */
     55#define KN02CA_MSR_PFORCE	(0xf<<21)	/* byte lane error force */
     56#define KN02CA_MSR_MABEN	(1<<20)		/* A side VFB address enable */
     57#define KN02CA_MSR_LASTBANK	(0x7<<17)	/* onboard RAM bank # */
     58
     59/*
     60 * I/O ASIC System Support Register bits.
     61 */
     62#define KN03CA_IO_SSR_RES_14	(1<<14)		/* unused */
     63#define KN03CA_IO_SSR_RES_13	(1<<13)		/* unused */
     64#define KN03CA_IO_SSR_ISDN_RST	(1<<12)		/* ~ISDN (Am79C30A) reset */
     65
     66#define KN03CA_IO_SSR_FLOPPY_RST (1<<7)		/* ~FDC (82077) reset */
     67#define KN03CA_IO_SSR_VIDEO_RST	(1<<6)		/* ~framebuffer reset */
     68#define KN03CA_IO_SSR_AB_RST	(1<<5)		/* ACCESS.bus reset */
     69#define KN03CA_IO_SSR_RES_4	(1<<4)		/* unused */
     70#define KN03CA_IO_SSR_RES_3	(1<<4)		/* unused */
     71#define KN03CA_IO_SSR_RES_2	(1<<2)		/* unused */
     72#define KN03CA_IO_SSR_RES_1	(1<<1)		/* unused */
     73#define KN03CA_IO_SSR_LED	(1<<0)		/* power LED */
     74
     75#endif /* __ASM_MIPS_DEC_KN02CA_H */