cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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i8259.h (2440B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 *	include/asm-mips/i8259.h
      4 *
      5 *	i8259A interrupt definitions.
      6 *
      7 *	Copyright (C) 2003  Maciej W. Rozycki
      8 *	Copyright (C) 2003  Ralf Baechle <ralf@linux-mips.org>
      9 */
     10#ifndef _ASM_I8259_H
     11#define _ASM_I8259_H
     12
     13#include <linux/compiler.h>
     14#include <linux/spinlock.h>
     15
     16#include <asm/io.h>
     17#include <irq.h>
     18
     19/* i8259A PIC registers */
     20#define PIC_MASTER_CMD		0x20
     21#define PIC_MASTER_IMR		0x21
     22#define PIC_MASTER_ISR		PIC_MASTER_CMD
     23#define PIC_MASTER_POLL		PIC_MASTER_ISR
     24#define PIC_MASTER_OCW3		PIC_MASTER_ISR
     25#define PIC_SLAVE_CMD		0xa0
     26#define PIC_SLAVE_IMR		0xa1
     27
     28/* i8259A PIC related value */
     29#define PIC_CASCADE_IR		2
     30#define MASTER_ICW4_DEFAULT	0x01
     31#define SLAVE_ICW4_DEFAULT	0x01
     32#define PIC_ICW4_AEOI		2
     33
     34extern raw_spinlock_t i8259A_lock;
     35
     36extern void make_8259A_irq(unsigned int irq);
     37
     38extern void init_i8259_irqs(void);
     39extern struct irq_domain *__init_i8259_irqs(struct device_node *node);
     40
     41/**
     42 * i8159_set_poll() - Override the i8259 polling function
     43 * @poll: pointer to platform-specific polling function
     44 *
     45 * Call this to override the generic i8259 polling function, which directly
     46 * accesses i8259 registers, with a platform specific one which may be faster
     47 * in cases where hardware provides a more optimal means of polling for an
     48 * interrupt.
     49 */
     50extern void i8259_set_poll(int (*poll)(void));
     51
     52/*
     53 * Do the traditional i8259 interrupt polling thing.  This is for the few
     54 * cases where no better interrupt acknowledge method is available and we
     55 * absolutely must touch the i8259.
     56 */
     57static inline int i8259_irq(void)
     58{
     59	int irq;
     60
     61	raw_spin_lock(&i8259A_lock);
     62
     63	/* Perform an interrupt acknowledge cycle on controller 1. */
     64	outb(0x0C, PIC_MASTER_CMD);		/* prepare for poll */
     65	irq = inb(PIC_MASTER_CMD) & 7;
     66	if (irq == PIC_CASCADE_IR) {
     67		/*
     68		 * Interrupt is cascaded so perform interrupt
     69		 * acknowledge on controller 2.
     70		 */
     71		outb(0x0C, PIC_SLAVE_CMD);		/* prepare for poll */
     72		irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
     73	}
     74
     75	if (unlikely(irq == 7)) {
     76		/*
     77		 * This may be a spurious interrupt.
     78		 *
     79		 * Read the interrupt status register (ISR). If the most
     80		 * significant bit is not set then there is no valid
     81		 * interrupt.
     82		 */
     83		outb(0x0B, PIC_MASTER_ISR);		/* ISR register */
     84		if(~inb(PIC_MASTER_ISR) & 0x80)
     85			irq = -1;
     86	}
     87
     88	raw_spin_unlock(&i8259A_lock);
     89
     90	return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
     91}
     92
     93#endif /* _ASM_I8259_H */