cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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inst.h (2398B)

      1/*
      2 * Format of an instruction in memory.
      3 *
      4 * This file is subject to the terms and conditions of the GNU General Public
      5 * License.  See the file "COPYING" in the main directory of this archive
      6 * for more details.
      7 *
      8 * Copyright (C) 1996, 2000 by Ralf Baechle
      9 * Copyright (C) 2006 by Thiemo Seufer
     10 */
     11#ifndef _ASM_INST_H
     12#define _ASM_INST_H
     13
     14#include <uapi/asm/inst.h>
     15
     16/* HACHACHAHCAHC ...  */
     17
     18/* In case some other massaging is needed, keep MIPSInst as wrapper */
     19
     20#define MIPSInst(x) x
     21
     22#define I_OPCODE_SFT	26
     23#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
     24
     25#define I_JTARGET_SFT	0
     26#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
     27
     28#define I_RS_SFT	21
     29#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
     30
     31#define I_RT_SFT	16
     32#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
     33
     34#define I_IMM_SFT	0
     35#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
     36#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
     37
     38#define I_CACHEOP_SFT	18
     39#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
     40
     41#define I_CACHESEL_SFT	16
     42#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
     43
     44#define I_RD_SFT	11
     45#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
     46
     47#define I_RE_SFT	6
     48#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)
     49
     50#define I_FUNC_SFT	0
     51#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)
     52
     53#define I_FFMT_SFT	21
     54#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)
     55
     56#define I_FT_SFT	16
     57#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)
     58
     59#define I_FS_SFT	11
     60#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)
     61
     62#define I_FD_SFT	6
     63#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)
     64
     65#define I_FR_SFT	21
     66#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)
     67
     68#define I_FMA_FUNC_SFT	3
     69#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x00000038) >> I_FMA_FUNC_SFT)
     70
     71#define I_FMA_FFMT_SFT	0
     72#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000007)
     73
     74typedef unsigned int mips_instruction;
     75
     76/* microMIPS instruction decode structure. Do NOT export!!! */
     77struct mm_decoded_insn {
     78	mips_instruction insn;
     79	mips_instruction next_insn;
     80	int pc_inc;
     81	int next_pc_inc;
     82	int micro_mips_mode;
     83};
     84
     85/* Recode table from 16-bit register notation to 32-bit GPR. Do NOT export!!! */
     86extern const int reg16to32[];
     87
     88#endif /* _ASM_INST_H */