cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

irq_gt641xx.h (2074B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 *  Galileo/Marvell GT641xx IRQ definitions.
      4 *
      5 *  Copyright (C) 2007  Yoichi Yuasa <yuasa@linux-mips.org>
      6 */
      7#ifndef _ASM_IRQ_GT641XX_H
      8#define _ASM_IRQ_GT641XX_H
      9
     10#ifndef GT641XX_IRQ_BASE
     11#define GT641XX_IRQ_BASE		8
     12#endif
     13
     14#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ		(GT641XX_IRQ_BASE + 1)
     15#define GT641XX_DMA_OUT_OF_RANGE_IRQ		(GT641XX_IRQ_BASE + 2)
     16#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ	(GT641XX_IRQ_BASE + 3)
     17#define GT641XX_DMA0_IRQ			(GT641XX_IRQ_BASE + 4)
     18#define GT641XX_DMA1_IRQ			(GT641XX_IRQ_BASE + 5)
     19#define GT641XX_DMA2_IRQ			(GT641XX_IRQ_BASE + 6)
     20#define GT641XX_DMA3_IRQ			(GT641XX_IRQ_BASE + 7)
     21#define GT641XX_TIMER0_IRQ			(GT641XX_IRQ_BASE + 8)
     22#define GT641XX_TIMER1_IRQ			(GT641XX_IRQ_BASE + 9)
     23#define GT641XX_TIMER2_IRQ			(GT641XX_IRQ_BASE + 10)
     24#define GT641XX_TIMER3_IRQ			(GT641XX_IRQ_BASE + 11)
     25#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ	(GT641XX_IRQ_BASE + 12)
     26#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ	(GT641XX_IRQ_BASE + 13)
     27#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ	(GT641XX_IRQ_BASE + 14)
     28#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ	(GT641XX_IRQ_BASE + 15)
     29#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ		(GT641XX_IRQ_BASE + 16)
     30#define GT641XX_MEMORY_ERROR_IRQ		(GT641XX_IRQ_BASE + 17)
     31#define GT641XX_PCI_0_MASTER_ABORT_IRQ		(GT641XX_IRQ_BASE + 18)
     32#define GT641XX_PCI_0_TARGET_ABORT_IRQ		(GT641XX_IRQ_BASE + 19)
     33#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ		(GT641XX_IRQ_BASE + 20)
     34#define GT641XX_CPU_INT0_IRQ			(GT641XX_IRQ_BASE + 21)
     35#define GT641XX_CPU_INT1_IRQ			(GT641XX_IRQ_BASE + 22)
     36#define GT641XX_CPU_INT2_IRQ			(GT641XX_IRQ_BASE + 23)
     37#define GT641XX_CPU_INT3_IRQ			(GT641XX_IRQ_BASE + 24)
     38#define GT641XX_CPU_INT4_IRQ			(GT641XX_IRQ_BASE + 25)
     39#define GT641XX_PCI_INT0_IRQ			(GT641XX_IRQ_BASE + 26)
     40#define GT641XX_PCI_INT1_IRQ			(GT641XX_IRQ_BASE + 27)
     41#define GT641XX_PCI_INT2_IRQ			(GT641XX_IRQ_BASE + 28)
     42#define GT641XX_PCI_INT3_IRQ			(GT641XX_IRQ_BASE + 29)
     43
     44extern void gt641xx_irq_dispatch(void);
     45extern void gt641xx_irq_init(void);
     46
     47#endif /* _ASM_IRQ_GT641XX_H */