cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cpu-feature-overrides.h (1417B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 *  Atheros AR231x/AR531x SoC specific CPU feature overrides
      4 *
      5 *  Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
      6 *
      7 *  This file was derived from: include/asm-mips/cpu-features.h
      8 *	Copyright (C) 2003, 2004 Ralf Baechle
      9 *	Copyright (C) 2004 Maciej W. Rozycki
     10 */
     11#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
     12#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
     13
     14/*
     15 * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
     16 */
     17#define cpu_has_tlb			1
     18#define cpu_has_4kex			1
     19#define cpu_has_3k_cache		0
     20#define cpu_has_4k_cache		1
     21#define cpu_has_sb1_cache		0
     22#define cpu_has_fpu			0
     23#define cpu_has_32fpr			0
     24#define cpu_has_counter			1
     25#define cpu_has_ejtag			1
     26
     27#if !defined(CONFIG_SOC_AR5312)
     28#  define cpu_has_llsc			1
     29#else
     30/*
     31 * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
     32 * ll/sc instructions.
     33 */
     34#  define cpu_has_llsc			0
     35#endif
     36
     37#define cpu_has_mips16			0
     38#define cpu_has_mips16e2		0
     39#define cpu_has_mdmx			0
     40#define cpu_has_mips3d			0
     41#define cpu_has_smartmips		0
     42
     43#define cpu_has_mips32r1		1
     44
     45#if !defined(CONFIG_SOC_AR5312)
     46#  define cpu_has_mips32r2		1
     47#endif
     48
     49#define cpu_has_mips64r1		0
     50#define cpu_has_mips64r2		0
     51
     52#define cpu_has_dsp			0
     53#define cpu_has_mipsmt			0
     54
     55#define cpu_has_64bits			0
     56#define cpu_has_64bit_zero_reg		0
     57#define cpu_has_64bit_gp_regs		0
     58
     59#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */