cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pci.h (1443B)


      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
      4 * Copyright (c) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
      5 */
      6
      7#ifndef __ASM_MACH_LOONGSON2EF_PCI_H_
      8#define __ASM_MACH_LOONGSON2EF_PCI_H_
      9
     10extern struct pci_ops loongson_pci_ops;
     11
     12/* this is an offset from mips_io_port_base */
     13#define LOONGSON_PCI_IO_START	0x00004000UL
     14
     15#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
     16
     17/*
     18 * we use address window2 to map cpu address space to pci space
     19 * window2: cpu [1G, 2G] -> pci [1G, 2G]
     20 * why not use window 0 & 1? because they are used by cpu when booting.
     21 * window0: cpu [0, 256M] -> ddr [0, 256M]
     22 * window1: cpu [256M, 512M] -> pci [256M, 512M]
     23 */
     24
     25/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */
     26#define LOONGSON_CPU_MEM_SRC	0x40000000ul		/* 1G */
     27#define LOONGSON_PCI_MEM_DST	LOONGSON_CPU_MEM_SRC
     28
     29#define LOONGSON_PCI_MEM_START	LOONGSON_PCI_MEM_DST
     30#define LOONGSON_PCI_MEM_END	(0x80000000ul-1)	/* 2G */
     31
     32#define MMAP_CPUTOPCI_SIZE	(LOONGSON_PCI_MEM_END - \
     33					LOONGSON_PCI_MEM_START + 1)
     34
     35#else	/* loongson2f/32bit & loongson2e */
     36
     37/* this pci memory space is mapped by pcimap in pci.c */
     38#define LOONGSON_PCI_MEM_START	LOONGSON_PCILO1_BASE
     39#define LOONGSON_PCI_MEM_END	(LOONGSON_PCILO1_BASE + 0x04000000 * 2)
     40
     41/* this is an offset from mips_io_port_base */
     42#define LOONGSON_PCI_IO_START	0x00004000UL
     43
     44#endif	/* !CONFIG_CPU_SUPPORTS_ADDRWINCFG */
     45
     46#endif /* !__ASM_MACH_LOONGSON2EF_PCI_H_ */