cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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loongson.h (9600B)


      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 * Copyright (C) 2009 Lemote, Inc.
      4 * Author: Wu Zhangjin <wuzhangjin@gmail.com>
      5 */
      6
      7#ifndef __ASM_MACH_LOONGSON64_LOONGSON_H
      8#define __ASM_MACH_LOONGSON64_LOONGSON_H
      9
     10#include <linux/io.h>
     11#include <linux/init.h>
     12#include <linux/irq.h>
     13#include <boot_param.h>
     14
     15enum loongson_fw_interface {
     16	LOONGSON_LEFI,
     17	LOONGSON_DTB,
     18};
     19
     20/* machine-specific boot configuration */
     21struct loongson_system_configuration {
     22	enum loongson_fw_interface fw_interface;
     23	u32 nr_cpus;
     24	u32 nr_nodes;
     25	int cores_per_node;
     26	int cores_per_package;
     27	u16 boot_cpu_id;
     28	u16 reserved_cpus_mask;
     29	enum loongson_cpu_type cputype;
     30	enum loongson_bridge_type bridgetype;
     31	u64 restart_addr;
     32	u64 poweroff_addr;
     33	u64 suspend_addr;
     34	u64 vgabios_addr;
     35	u32 dma_mask_bits;
     36	u64 workarounds;
     37	void (*early_config)(void);
     38};
     39
     40/* machine-specific reboot/halt operation */
     41extern void mach_prepare_reboot(void);
     42extern void mach_prepare_shutdown(void);
     43
     44/* environment arguments from bootloader */
     45extern u32 cpu_clock_freq;
     46extern u32 memsize, highmemsize;
     47extern const struct plat_smp_ops loongson3_smp_ops;
     48
     49/* loongson-specific command line, env and memory initialization */
     50extern void __init prom_dtb_init_env(void);
     51extern void __init prom_lefi_init_env(void);
     52extern void __init szmem(unsigned int node);
     53extern void *loongson_fdt_blob;
     54
     55/* irq operation functions */
     56extern void mach_irq_dispatch(unsigned int pending);
     57extern int mach_i8259_irq(void);
     58
     59/* We need this in some places... */
     60#define delay() ({		\
     61	int x;				\
     62	for (x = 0; x < 100000; x++)	\
     63		__asm__ __volatile__(""); \
     64})
     65
     66#define LOONGSON_REG(x) \
     67	(*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
     68
     69#define LOONGSON3_REG8(base, x) \
     70	(*(volatile u8 *)((char *)TO_UNCAC(base) + (x)))
     71
     72#define LOONGSON3_REG32(base, x) \
     73	(*(volatile u32 *)((char *)TO_UNCAC(base) + (x)))
     74
     75#define LOONGSON_FLASH_BASE	0x1c000000
     76#define LOONGSON_FLASH_SIZE	0x02000000	/* 32M */
     77#define LOONGSON_FLASH_TOP	(LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
     78
     79#define LOONGSON_LIO0_BASE	0x1e000000
     80#define LOONGSON_LIO0_SIZE	0x01C00000	/* 28M */
     81#define LOONGSON_LIO0_TOP	(LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
     82
     83#define LOONGSON_BOOT_BASE	0x1fc00000
     84#define LOONGSON_BOOT_SIZE	0x00100000	/* 1M */
     85#define LOONGSON_BOOT_TOP	(LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
     86#define LOONGSON_REG_BASE	0x1fe00000
     87#define LOONGSON_REG_SIZE	0x00100000	/* 256Bytes + 256Bytes + ??? */
     88#define LOONGSON_REG_TOP	(LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
     89/* Loongson-3 specific registers */
     90#define LOONGSON3_REG_BASE	0x3ff00000
     91#define LOONGSON3_REG_SIZE	0x00100000	/* 256Bytes + 256Bytes + ??? */
     92#define LOONGSON3_REG_TOP	(LOONGSON3_REG_BASE+LOONGSON3_REG_SIZE-1)
     93
     94#define LOONGSON_LIO1_BASE	0x1ff00000
     95#define LOONGSON_LIO1_SIZE	0x00100000	/* 1M */
     96#define LOONGSON_LIO1_TOP	(LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
     97
     98#define LOONGSON_PCILO0_BASE	0x10000000
     99#define LOONGSON_PCILO1_BASE	0x14000000
    100#define LOONGSON_PCILO2_BASE	0x18000000
    101#define LOONGSON_PCILO_BASE	LOONGSON_PCILO0_BASE
    102#define LOONGSON_PCILO_SIZE	0x0c000000	/* 64M * 3 */
    103#define LOONGSON_PCILO_TOP	(LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
    104
    105#define LOONGSON_PCICFG_BASE	0x1fe80000
    106#define LOONGSON_PCICFG_SIZE	0x00000800	/* 2K */
    107#define LOONGSON_PCICFG_TOP	(LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
    108
    109#define LOONGSON_PCIIO_BASE	loongson_sysconf.pci_io_base
    110
    111#define LOONGSON_PCIIO_SIZE	0x00100000	/* 1M */
    112#define LOONGSON_PCIIO_TOP	(LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
    113
    114/* Loongson Register Bases */
    115
    116#define LOONGSON_PCICONFIGBASE	0x00
    117#define LOONGSON_REGBASE	0x100
    118
    119/* PCI Configuration Registers */
    120
    121#define LOONGSON_PCI_REG(x)	LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
    122#define LOONGSON_PCIDID		LOONGSON_PCI_REG(0x00)
    123#define LOONGSON_PCICMD		LOONGSON_PCI_REG(0x04)
    124#define LOONGSON_PCICLASS	LOONGSON_PCI_REG(0x08)
    125#define LOONGSON_PCILTIMER	LOONGSON_PCI_REG(0x0c)
    126#define LOONGSON_PCIBASE0	LOONGSON_PCI_REG(0x10)
    127#define LOONGSON_PCIBASE1	LOONGSON_PCI_REG(0x14)
    128#define LOONGSON_PCIBASE2	LOONGSON_PCI_REG(0x18)
    129#define LOONGSON_PCIBASE3	LOONGSON_PCI_REG(0x1c)
    130#define LOONGSON_PCIBASE4	LOONGSON_PCI_REG(0x20)
    131#define LOONGSON_PCIEXPRBASE	LOONGSON_PCI_REG(0x30)
    132#define LOONGSON_PCIINT		LOONGSON_PCI_REG(0x3c)
    133
    134#define LOONGSON_PCI_ISR4C	LOONGSON_PCI_REG(0x4c)
    135
    136#define LOONGSON_PCICMD_PERR_CLR	0x80000000
    137#define LOONGSON_PCICMD_SERR_CLR	0x40000000
    138#define LOONGSON_PCICMD_MABORT_CLR	0x20000000
    139#define LOONGSON_PCICMD_MTABORT_CLR	0x10000000
    140#define LOONGSON_PCICMD_TABORT_CLR	0x08000000
    141#define LOONGSON_PCICMD_MPERR_CLR	0x01000000
    142#define LOONGSON_PCICMD_PERRRESPEN	0x00000040
    143#define LOONGSON_PCICMD_ASTEPEN		0x00000080
    144#define LOONGSON_PCICMD_SERREN		0x00000100
    145#define LOONGSON_PCILTIMER_BUSLATENCY	0x0000ff00
    146#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT	8
    147
    148/* Loongson h/w Configuration */
    149
    150#define LOONGSON_GENCFG_OFFSET		0x4
    151#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
    152
    153#define LOONGSON_GENCFG_DEBUGMODE	0x00000001
    154#define LOONGSON_GENCFG_SNOOPEN		0x00000002
    155#define LOONGSON_GENCFG_CPUSELFRESET	0x00000004
    156
    157#define LOONGSON_GENCFG_FORCE_IRQA	0x00000008
    158#define LOONGSON_GENCFG_IRQA_ISOUT	0x00000010
    159#define LOONGSON_GENCFG_IRQA_FROM_INT1	0x00000020
    160#define LOONGSON_GENCFG_BYTESWAP	0x00000040
    161
    162#define LOONGSON_GENCFG_UNCACHED	0x00000080
    163#define LOONGSON_GENCFG_PREFETCHEN	0x00000100
    164#define LOONGSON_GENCFG_WBEHINDEN	0x00000200
    165#define LOONGSON_GENCFG_CACHEALG	0x00000c00
    166#define LOONGSON_GENCFG_CACHEALG_SHIFT	10
    167#define LOONGSON_GENCFG_PCIQUEUE	0x00001000
    168#define LOONGSON_GENCFG_CACHESTOP	0x00002000
    169#define LOONGSON_GENCFG_MSTRBYTESWAP	0x00004000
    170#define LOONGSON_GENCFG_BUSERREN	0x00008000
    171#define LOONGSON_GENCFG_NORETRYTIMEOUT	0x00010000
    172#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT	0x00020000
    173
    174/* PCI address map control */
    175
    176#define LOONGSON_PCIMAP			LOONGSON_REG(LOONGSON_REGBASE + 0x10)
    177#define LOONGSON_PCIMEMBASECFG		LOONGSON_REG(LOONGSON_REGBASE + 0x14)
    178#define LOONGSON_PCIMAP_CFG		LOONGSON_REG(LOONGSON_REGBASE + 0x18)
    179
    180/* GPIO Regs - r/w */
    181
    182#define LOONGSON_GPIODATA		LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
    183#define LOONGSON_GPIOIE			LOONGSON_REG(LOONGSON_REGBASE + 0x20)
    184
    185/* ICU Configuration Regs - r/w */
    186
    187#define LOONGSON_INTEDGE		LOONGSON_REG(LOONGSON_REGBASE + 0x24)
    188#define LOONGSON_INTSTEER		LOONGSON_REG(LOONGSON_REGBASE + 0x28)
    189#define LOONGSON_INTPOL			LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
    190
    191/* ICU Enable Regs - IntEn & IntISR are r/o. */
    192
    193#define LOONGSON_INTENSET		LOONGSON_REG(LOONGSON_REGBASE + 0x30)
    194#define LOONGSON_INTENCLR		LOONGSON_REG(LOONGSON_REGBASE + 0x34)
    195#define LOONGSON_INTEN			LOONGSON_REG(LOONGSON_REGBASE + 0x38)
    196#define LOONGSON_INTISR			LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
    197
    198/* ICU */
    199#define LOONGSON_ICU_MBOXES		0x0000000f
    200#define LOONGSON_ICU_MBOXES_SHIFT	0
    201#define LOONGSON_ICU_DMARDY		0x00000010
    202#define LOONGSON_ICU_DMAEMPTY		0x00000020
    203#define LOONGSON_ICU_COPYRDY		0x00000040
    204#define LOONGSON_ICU_COPYEMPTY		0x00000080
    205#define LOONGSON_ICU_COPYERR		0x00000100
    206#define LOONGSON_ICU_PCIIRQ		0x00000200
    207#define LOONGSON_ICU_MASTERERR		0x00000400
    208#define LOONGSON_ICU_SYSTEMERR		0x00000800
    209#define LOONGSON_ICU_DRAMPERR		0x00001000
    210#define LOONGSON_ICU_RETRYERR		0x00002000
    211#define LOONGSON_ICU_GPIOS		0x01ff0000
    212#define LOONGSON_ICU_GPIOS_SHIFT		16
    213#define LOONGSON_ICU_GPINS		0x7e000000
    214#define LOONGSON_ICU_GPINS_SHIFT		25
    215#define LOONGSON_ICU_MBOX(N)		(1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
    216#define LOONGSON_ICU_GPIO(N)		(1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
    217#define LOONGSON_ICU_GPIN(N)		(1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
    218
    219/* PCI prefetch window base & mask */
    220
    221#define LOONGSON_MEM_WIN_BASE_L		LOONGSON_REG(LOONGSON_REGBASE + 0x40)
    222#define LOONGSON_MEM_WIN_BASE_H		LOONGSON_REG(LOONGSON_REGBASE + 0x44)
    223#define LOONGSON_MEM_WIN_MASK_L		LOONGSON_REG(LOONGSON_REGBASE + 0x48)
    224#define LOONGSON_MEM_WIN_MASK_H		LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
    225
    226/* PCI_Hit*_Sel_* */
    227
    228#define LOONGSON_PCI_HIT0_SEL_L		LOONGSON_REG(LOONGSON_REGBASE + 0x50)
    229#define LOONGSON_PCI_HIT0_SEL_H		LOONGSON_REG(LOONGSON_REGBASE + 0x54)
    230#define LOONGSON_PCI_HIT1_SEL_L		LOONGSON_REG(LOONGSON_REGBASE + 0x58)
    231#define LOONGSON_PCI_HIT1_SEL_H		LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
    232#define LOONGSON_PCI_HIT2_SEL_L		LOONGSON_REG(LOONGSON_REGBASE + 0x60)
    233#define LOONGSON_PCI_HIT2_SEL_H		LOONGSON_REG(LOONGSON_REGBASE + 0x64)
    234
    235/* PXArb Config & Status */
    236
    237#define LOONGSON_PXARB_CFG		LOONGSON_REG(LOONGSON_REGBASE + 0x68)
    238#define LOONGSON_PXARB_STATUS		LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
    239
    240#define MAX_PACKAGES 4
    241
    242/* Chip Config registor of each physical cpu package, PRid >= Loongson-2F */
    243extern u64 loongson_chipcfg[MAX_PACKAGES];
    244#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
    245
    246/* Chip Temperature registor of each physical cpu package, PRid >= Loongson-3A */
    247extern u64 loongson_chiptemp[MAX_PACKAGES];
    248#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id]))
    249
    250/* Freq Control register of each physical cpu package, PRid >= Loongson-3B */
    251extern u64 loongson_freqctrl[MAX_PACKAGES];
    252#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))
    253
    254/* pcimap */
    255
    256#define LOONGSON_PCIMAP_PCIMAP_LO0	0x0000003f
    257#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT	0
    258#define LOONGSON_PCIMAP_PCIMAP_LO1	0x00000fc0
    259#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT	6
    260#define LOONGSON_PCIMAP_PCIMAP_LO2	0x0003f000
    261#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT	12
    262#define LOONGSON_PCIMAP_PCIMAP_2	0x00040000
    263#define LOONGSON_PCIMAP_WIN(WIN, ADDR)	\
    264	((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
    265
    266#endif /* __ASM_MACH_LOONGSON64_LOONGSON_H */