cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pic32.h (977B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Joshua Henderson <joshua.henderson@microchip.com>
      4 * Copyright (C) 2015 Microchip Technology Inc.  All rights reserved.
      5 */
      6#ifndef _ASM_MACH_PIC32_H
      7#define _ASM_MACH_PIC32_H
      8
      9#include <linux/io.h>
     10
     11/*
     12 * PIC32 register offsets for SET/CLR/INV where supported.
     13 */
     14#define PIC32_CLR(_reg)		((_reg) + 0x04)
     15#define PIC32_SET(_reg)		((_reg) + 0x08)
     16#define PIC32_INV(_reg)		((_reg) + 0x0C)
     17
     18/*
     19 * PIC32 Base Register Offsets
     20 */
     21#define PIC32_BASE_CONFIG	0x1f800000
     22#define PIC32_BASE_OSC		0x1f801200
     23#define PIC32_BASE_RESET	0x1f801240
     24#define PIC32_BASE_PPS		0x1f801400
     25#define PIC32_BASE_UART		0x1f822000
     26#define PIC32_BASE_PORT		0x1f860000
     27#define PIC32_BASE_DEVCFG2	0x1fc4ff44
     28
     29/*
     30 * Register unlock sequence required for some register access.
     31 */
     32void pic32_syskey_unlock_debug(const char *fn, const ulong ln);
     33#define pic32_syskey_unlock()	\
     34	pic32_syskey_unlock_debug(__func__, __LINE__)
     35
     36#endif /* _ASM_MACH_PIC32_H */