cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rt288x.h (1076B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 *
      4 * Parts of this file are based on Ralink's 2.6.21 BSP
      5 *
      6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
      7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
      8 * Copyright (C) 2013 John Crispin <john@phrozen.org>
      9 */
     10
     11#ifndef _RT288X_REGS_H_
     12#define _RT288X_REGS_H_
     13
     14#define RT2880_SYSC_BASE		0x00300000
     15
     16#define SYSC_REG_CHIP_NAME0		0x00
     17#define SYSC_REG_CHIP_NAME1		0x04
     18#define SYSC_REG_CHIP_ID		0x0c
     19#define SYSC_REG_SYSTEM_CONFIG		0x10
     20#define SYSC_REG_CLKCFG			0x30
     21
     22#define RT2880_CHIP_NAME0		0x38325452
     23#define RT2880_CHIP_NAME1		0x20203038
     24
     25#define CHIP_ID_ID_MASK			0xff
     26#define CHIP_ID_ID_SHIFT		8
     27#define CHIP_ID_REV_MASK		0xff
     28
     29#define SYSTEM_CONFIG_CPUCLK_SHIFT	20
     30#define SYSTEM_CONFIG_CPUCLK_MASK	0x3
     31#define SYSTEM_CONFIG_CPUCLK_250	0x0
     32#define SYSTEM_CONFIG_CPUCLK_266	0x1
     33#define SYSTEM_CONFIG_CPUCLK_280	0x2
     34#define SYSTEM_CONFIG_CPUCLK_300	0x3
     35
     36#define CLKCFG_SRAM_CS_N_WDT		BIT(9)
     37
     38#define RT2880_SDRAM_BASE		0x08000000
     39#define RT2880_MEM_SIZE_MIN		2
     40#define RT2880_MEM_SIZE_MAX		128
     41
     42#endif