cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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gpio.h (2131B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Copyright 2002 Integrated Device Technology, Inc.
      4 *	All rights reserved.
      5 *
      6 * GPIO register definition.
      7 *
      8 * Author : ryan.holmQVist@idt.com
      9 * Date	  : 20011005
     10 * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
     11 * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
     12 */
     13
     14#ifndef _RC32434_GPIO_H_
     15#define _RC32434_GPIO_H_
     16
     17struct rb532_gpio_reg {
     18	u32   gpiofunc;	  /* GPIO Function Register
     19			   * gpiofunc[x]==0 bit = gpio
     20			   * func[x]==1	 bit = altfunc
     21			   */
     22	u32   gpiocfg;	  /* GPIO Configuration Register
     23			   * gpiocfg[x]==0 bit = input
     24			   * gpiocfg[x]==1 bit = output
     25			   */
     26	u32   gpiod;	  /* GPIO Data Register
     27			   * gpiod[x] read/write gpio pinX status
     28			   */
     29	u32   gpioilevel; /* GPIO Interrupt Status Register
     30			   * interrupt level (see gpioistat)
     31			   */
     32	u32   gpioistat;  /* Gpio Interrupt Status Register
     33			   * istat[x] = (gpiod[x] == level[x])
     34			   * cleared in ISR (STICKY bits)
     35			   */
     36	u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
     37};
     38
     39/* UART GPIO signals */
     40#define RC32434_UART0_SOUT	(1 << 0)
     41#define RC32434_UART0_SIN	(1 << 1)
     42#define RC32434_UART0_RTS	(1 << 2)
     43#define RC32434_UART0_CTS	(1 << 3)
     44
     45/* M & P bus GPIO signals */
     46#define RC32434_MP_BIT_22	(1 << 4)
     47#define RC32434_MP_BIT_23	(1 << 5)
     48#define RC32434_MP_BIT_24	(1 << 6)
     49#define RC32434_MP_BIT_25	(1 << 7)
     50
     51/* CPU GPIO signals */
     52#define RC32434_CPU_GPIO	(1 << 8)
     53
     54/* Reserved GPIO signals */
     55#define RC32434_AF_SPARE_6	(1 << 9)
     56#define RC32434_AF_SPARE_4	(1 << 10)
     57#define RC32434_AF_SPARE_3	(1 << 11)
     58#define RC32434_AF_SPARE_2	(1 << 12)
     59
     60/* PCI messaging unit */
     61#define RC32434_PCI_MSU_GPIO	(1 << 13)
     62
     63/* NAND GPIO signals */
     64#define GPIO_RDY		8
     65#define GPIO_WPX	9
     66#define GPIO_ALE		10
     67#define GPIO_CLE		11
     68
     69/* Compact Flash GPIO pin */
     70#define CF_GPIO_NUM		13
     71
     72/* S1 button GPIO (shared with UART0_SIN) */
     73#define GPIO_BTN_S1		1
     74
     75extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
     76extern void rb532_gpio_set_istat(int bit, unsigned gpio);
     77extern void rb532_gpio_set_func(unsigned gpio);
     78
     79#endif /* _RC32434_GPIO_H_ */