piix4.h (2130B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Carsten Langgaard, carstenl@mips.com 4 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 5 * Copyright (C) 2013 Imagination Technologies Ltd. 6 * 7 * Register definitions for Intel PIIX4 South Bridge Device. 8 */ 9#ifndef __ASM_MIPS_BOARDS_PIIX4_H 10#define __ASM_MIPS_BOARDS_PIIX4_H 11 12/* PIRQX Route Control */ 13#define PIIX4_FUNC0_PIRQRC 0x60 14#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_DISABLE (1 << 7) 15#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MASK 0xf 16#define PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX 16 17/* SERIRQ Control */ 18#define PIIX4_FUNC0_SERIRQC 0x64 19#define PIIX4_FUNC0_SERIRQC_EN (1 << 7) 20#define PIIX4_FUNC0_SERIRQC_CONT (1 << 6) 21/* Top Of Memory */ 22#define PIIX4_FUNC0_TOM 0x69 23#define PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK 0xf0 24/* Deterministic Latency Control */ 25#define PIIX4_FUNC0_DLC 0x82 26#define PIIX4_FUNC0_DLC_USBPR_EN (1 << 2) 27#define PIIX4_FUNC0_DLC_PASSIVE_RELEASE_EN (1 << 1) 28#define PIIX4_FUNC0_DLC_DELAYED_TRANSACTION_EN (1 << 0) 29/* General Configuration */ 30#define PIIX4_FUNC0_GENCFG 0xb0 31#define PIIX4_FUNC0_GENCFG_SERIRQ (1 << 16) 32 33/* IDE Timing */ 34#define PIIX4_FUNC1_IDETIM_PRIMARY_LO 0x40 35#define PIIX4_FUNC1_IDETIM_PRIMARY_HI 0x41 36#define PIIX4_FUNC1_IDETIM_PRIMARY_HI_IDE_DECODE_EN (1 << 7) 37#define PIIX4_FUNC1_IDETIM_SECONDARY_LO 0x42 38#define PIIX4_FUNC1_IDETIM_SECONDARY_HI 0x43 39#define PIIX4_FUNC1_IDETIM_SECONDARY_HI_IDE_DECODE_EN (1 << 7) 40 41/* Power Management Configuration Space */ 42#define PIIX4_FUNC3_PMBA 0x40 43#define PIIX4_FUNC3_PMREGMISC 0x80 44#define PIIX4_FUNC3_PMREGMISC_EN (1 << 0) 45 46/* Power Management IO Space */ 47#define PIIX4_FUNC3IO_PMSTS 0x00 48#define PIIX4_FUNC3IO_PMSTS_PWRBTN_STS (1 << 8) 49#define PIIX4_FUNC3IO_PMCNTRL 0x04 50#define PIIX4_FUNC3IO_PMCNTRL_SUS_EN (1 << 13) 51#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP (0x7 << 10) 52#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_SOFF (0x0 << 10) 53#define PIIX4_FUNC3IO_PMCNTRL_SUS_TYP_STR (0x1 << 10) 54 55/* Data for magic special PCI cycle */ 56#define PIIX4_SUSPEND_MAGIC 0x00120002 57 58#endif /* __ASM_MIPS_BOARDS_PIIX4_H */