cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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regdef.h (2693B)


      1/*
      2 * This file is subject to the terms and conditions of the GNU General Public
      3 * License.  See the file "COPYING" in the main directory of this archive
      4 * for more details.
      5 *
      6 * Copyright (C) 1985 MIPS Computer Systems, Inc.
      7 * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
      8 * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
      9 * Copyright (C) 2011 Wind River Systems,
     10 *   written by Ralf Baechle <ralf@linux-mips.org>
     11 */
     12#ifndef _ASM_REGDEF_H
     13#define _ASM_REGDEF_H
     14
     15#include <asm/sgidefs.h>
     16
     17#if _MIPS_SIM == _MIPS_SIM_ABI32
     18
     19/*
     20 * Symbolic register names for 32 bit ABI
     21 */
     22#define zero	$0	/* wired zero */
     23#define AT	$1	/* assembler temp  - uppercase because of ".set at" */
     24#define v0	$2	/* return value */
     25#define v1	$3
     26#define a0	$4	/* argument registers */
     27#define a1	$5
     28#define a2	$6
     29#define a3	$7
     30#define t0	$8	/* caller saved */
     31#define t1	$9
     32#define t2	$10
     33#define t3	$11
     34#define t4	$12
     35#define ta0	$12
     36#define t5	$13
     37#define ta1	$13
     38#define t6	$14
     39#define ta2	$14
     40#define t7	$15
     41#define ta3	$15
     42#define s0	$16	/* callee saved */
     43#define s1	$17
     44#define s2	$18
     45#define s3	$19
     46#define s4	$20
     47#define s5	$21
     48#define s6	$22
     49#define s7	$23
     50#define t8	$24	/* caller saved */
     51#define t9	$25
     52#define jp	$25	/* PIC jump register */
     53#define k0	$26	/* kernel scratch */
     54#define k1	$27
     55#define gp	$28	/* global pointer */
     56#define sp	$29	/* stack pointer */
     57#define fp	$30	/* frame pointer */
     58#define s8	$30	/* same like fp! */
     59#define ra	$31	/* return address */
     60
     61#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
     62
     63#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
     64
     65#define zero	$0	/* wired zero */
     66#define AT	$at	/* assembler temp - uppercase because of ".set at" */
     67#define v0	$2	/* return value - caller saved */
     68#define v1	$3
     69#define a0	$4	/* argument registers */
     70#define a1	$5
     71#define a2	$6
     72#define a3	$7
     73#define a4	$8	/* arg reg 64 bit; caller saved in 32 bit */
     74#define ta0	$8
     75#define a5	$9
     76#define ta1	$9
     77#define a6	$10
     78#define ta2	$10
     79#define a7	$11
     80#define ta3	$11
     81#define t0	$12	/* caller saved */
     82#define t1	$13
     83#define t2	$14
     84#define t3	$15
     85#define s0	$16	/* callee saved */
     86#define s1	$17
     87#define s2	$18
     88#define s3	$19
     89#define s4	$20
     90#define s5	$21
     91#define s6	$22
     92#define s7	$23
     93#define t8	$24	/* caller saved */
     94#define t9	$25	/* callee address for PIC/temp */
     95#define jp	$25	/* PIC jump register */
     96#define k0	$26	/* kernel temporary */
     97#define k1	$27
     98#define gp	$28	/* global pointer - caller saved for PIC */
     99#define sp	$29	/* stack pointer */
    100#define fp	$30	/* frame pointer */
    101#define s8	$30	/* callee saved */
    102#define ra	$31	/* return address */
    103
    104#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
    105
    106#endif /* _ASM_REGDEF_H */