cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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carmel.h (1057B)


      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 * Copyright (C) 2002 Broadcom Corporation
      4 */
      5#ifndef __ASM_SIBYTE_CARMEL_H
      6#define __ASM_SIBYTE_CARMEL_H
      7
      8#include <asm/sibyte/sb1250.h>
      9#include <asm/sibyte/sb1250_int.h>
     10
     11#define SIBYTE_BOARD_NAME "Carmel"
     12
     13#define GPIO_PHY_INTERRUPT	2
     14#define GPIO_NONMASKABLE_INT	3
     15#define GPIO_CF_INSERTED	6
     16#define GPIO_MONTEREY_RESET	7
     17#define GPIO_QUADUART_INT	8
     18#define GPIO_CF_INT		9
     19#define GPIO_FPGA_CCLK		10
     20#define GPIO_FPGA_DOUT		11
     21#define GPIO_FPGA_DIN		12
     22#define GPIO_FPGA_PGM		13
     23#define GPIO_FPGA_DONE		14
     24#define GPIO_FPGA_INIT		15
     25
     26#define LEDS_CS			2
     27#define LEDS_PHYS		0x100C0000
     28#define MLEDS_CS		3
     29#define MLEDS_PHYS		0x100A0000
     30#define UART_CS			4
     31#define UART_PHYS		0x100D0000
     32#define ARAVALI_CS		5
     33#define ARAVALI_PHYS		0x11000000
     34#define IDE_CS			6
     35#define IDE_PHYS		0x100B0000
     36#define ARAVALI2_CS		7
     37#define ARAVALI2_PHYS		0x100E0000
     38
     39#if defined(CONFIG_SIBYTE_CARMEL)
     40#define K_GPIO_GB_IDE	9
     41#define K_INT_GB_IDE	(K_INT_GPIO_0 + K_GPIO_GB_IDE)
     42#endif
     43
     44
     45#endif /* __ASM_SIBYTE_CARMEL_H */