cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intr.h (2663B)

      1/*
      2 * This file is subject to the terms and conditions of the GNU General Public
      3 * License.  See the file "COPYING" in the main directory of this archive
      4 * for more details.
      5 *
      6 * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
      7 */
      8#ifndef __ASM_SN_INTR_H
      9#define __ASM_SN_INTR_H
     10
     11/*
     12 * Macros to manipulate the interrupt register on the calling hub chip.
     13 */
     14
     15#define LOCAL_HUB_SEND_INTR(level)				\
     16	LOCAL_HUB_S(PI_INT_PEND_MOD, (0x100 | (level)))
     17#define REMOTE_HUB_SEND_INTR(hub, level)			\
     18	REMOTE_HUB_S((hub), PI_INT_PEND_MOD, (0x100 | (level)))
     19
     20/*
     21 * When clearing the interrupt, make sure this clear does make it
     22 * to the hub. Otherwise we could end up losing interrupts.
     23 * We do an uncached load of the int_pend0 register to ensure this.
     24 */
     25
     26#define LOCAL_HUB_CLR_INTR(level)				\
     27do {								\
     28	LOCAL_HUB_S(PI_INT_PEND_MOD, (level));			\
     29	LOCAL_HUB_L(PI_INT_PEND0);				\
     30} while (0);
     31
     32#define REMOTE_HUB_CLR_INTR(hub, level)				\
     33do {								\
     34	nasid_t	 __hub = (hub);					\
     35								\
     36	REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level));		\
     37	REMOTE_HUB_L(__hub, PI_INT_PEND0);			\
     38} while (0);
     39
     40/*
     41 * Hard-coded interrupt levels:
     42 */
     43
     44/*
     45 *	L0 = SW1
     46 *	L1 = SW2
     47 *	L2 = INT_PEND0
     48 *	L3 = INT_PEND1
     49 *	L4 = RTC
     50 *	L5 = Profiling Timer
     51 *	L6 = Hub Errors
     52 *	L7 = Count/Compare (T5 counters)
     53 */
     54
     55
     56/*
     57 * INT_PEND0 hard-coded bits.
     58 */
     59
     60/*
     61 * INT_PEND0 bits determined by hardware:
     62 */
     63#define RESERVED_INTR		 0	/* What is this bit? */
     64#define GFX_INTR_A		 1
     65#define GFX_INTR_B		 2
     66#define PG_MIG_INTR		 3
     67#define UART_INTR		 4
     68#define CC_PEND_A		 5
     69#define CC_PEND_B		 6
     70
     71/*
     72 * INT_PEND0 used by the kernel for itself ...
     73 */
     74#define CPU_RESCHED_A_IRQ	 7
     75#define CPU_RESCHED_B_IRQ	 8
     76#define CPU_CALL_A_IRQ		 9
     77#define CPU_CALL_B_IRQ		10
     78
     79/*
     80 * INT_PEND1 hard-coded bits:
     81 */
     82#define NI_BRDCAST_ERR_A	39
     83#define NI_BRDCAST_ERR_B	40
     84
     85#define LLP_PFAIL_INTR_A	41	/* see ml/SN/SN0/sysctlr.c */
     86#define LLP_PFAIL_INTR_B	42
     87
     88#define TLB_INTR_A		43	/* used for tlb flush random */
     89#define TLB_INTR_B		44
     90
     91#define IP27_INTR_0		45	/* Reserved for PROM use */
     92#define IP27_INTR_1		46	/* do not use in Kernel */
     93#define IP27_INTR_2		47
     94#define IP27_INTR_3		48
     95#define IP27_INTR_4		49
     96#define IP27_INTR_5		50
     97#define IP27_INTR_6		51
     98#define IP27_INTR_7		52
     99
    100#define BRIDGE_ERROR_INTR	53	/* Setup by PROM to catch	*/
    101					/* Bridge Errors */
    102#define DEBUG_INTR_A		54
    103#define DEBUG_INTR_B		55	/* Used by symmon to stop all cpus */
    104#define IO_ERROR_INTR		57	/* Setup by PROM */
    105#define CLK_ERR_INTR		58
    106#define COR_ERR_INTR_A		59
    107#define COR_ERR_INTR_B		60
    108#define MD_COR_ERR_INTR		61
    109#define NI_ERROR_INTR		62
    110#define MSC_PANIC_INTR		63
    111
    112#endif /* __ASM_SN_INTR_H */