cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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irq.h (2875B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 * include/asm-mips/vr41xx/irq.h
      4 *
      5 * Interrupt numbers for NEC VR4100 series.
      6 *
      7 * Copyright (C) 1999 Michael Klar
      8 * Copyright (C) 2001, 2002 Paul Mundt
      9 * Copyright (C) 2002 MontaVista Software, Inc.
     10 * Copyright (C) 2002 TimeSys Corp.
     11 * Copyright (C) 2003-2006 Yoichi Yuasa <yuasa@linux-mips.org>
     12 */
     13#ifndef __NEC_VR41XX_IRQ_H
     14#define __NEC_VR41XX_IRQ_H
     15
     16/*
     17 * CPU core Interrupt Numbers
     18 */
     19#define MIPS_CPU_IRQ_BASE	0
     20#define MIPS_CPU_IRQ(x)		(MIPS_CPU_IRQ_BASE + (x))
     21#define MIPS_SOFTINT0_IRQ	MIPS_CPU_IRQ(0)
     22#define MIPS_SOFTINT1_IRQ	MIPS_CPU_IRQ(1)
     23#define INT0_IRQ		MIPS_CPU_IRQ(2)
     24#define INT1_IRQ		MIPS_CPU_IRQ(3)
     25#define INT2_IRQ		MIPS_CPU_IRQ(4)
     26#define INT3_IRQ		MIPS_CPU_IRQ(5)
     27#define INT4_IRQ		MIPS_CPU_IRQ(6)
     28#define TIMER_IRQ		MIPS_CPU_IRQ(7)
     29
     30/*
     31 * SYINT1 Interrupt Numbers
     32 */
     33#define SYSINT1_IRQ_BASE	8
     34#define SYSINT1_IRQ(x)		(SYSINT1_IRQ_BASE + (x))
     35#define BATTRY_IRQ		SYSINT1_IRQ(0)
     36#define POWER_IRQ		SYSINT1_IRQ(1)
     37#define RTCLONG1_IRQ		SYSINT1_IRQ(2)
     38#define ELAPSEDTIME_IRQ		SYSINT1_IRQ(3)
     39/* RFU */
     40#define PIU_IRQ			SYSINT1_IRQ(5)
     41#define AIU_IRQ			SYSINT1_IRQ(6)
     42#define KIU_IRQ			SYSINT1_IRQ(7)
     43#define GIUINT_IRQ		SYSINT1_IRQ(8)
     44#define SIU_IRQ			SYSINT1_IRQ(9)
     45#define BUSERR_IRQ		SYSINT1_IRQ(10)
     46#define SOFTINT_IRQ		SYSINT1_IRQ(11)
     47#define CLKRUN_IRQ		SYSINT1_IRQ(12)
     48#define DOZEPIU_IRQ		SYSINT1_IRQ(13)
     49#define SYSINT1_IRQ_LAST	DOZEPIU_IRQ
     50
     51/*
     52 * SYSINT2 Interrupt Numbers
     53 */
     54#define SYSINT2_IRQ_BASE	24
     55#define SYSINT2_IRQ(x)		(SYSINT2_IRQ_BASE + (x))
     56#define RTCLONG2_IRQ		SYSINT2_IRQ(0)
     57#define LED_IRQ			SYSINT2_IRQ(1)
     58#define HSP_IRQ			SYSINT2_IRQ(2)
     59#define TCLOCK_IRQ		SYSINT2_IRQ(3)
     60#define FIR_IRQ			SYSINT2_IRQ(4)
     61#define CEU_IRQ			SYSINT2_IRQ(4)	/* same number as FIR_IRQ */
     62#define DSIU_IRQ		SYSINT2_IRQ(5)
     63#define PCI_IRQ			SYSINT2_IRQ(6)
     64#define SCU_IRQ			SYSINT2_IRQ(7)
     65#define CSI_IRQ			SYSINT2_IRQ(8)
     66#define BCU_IRQ			SYSINT2_IRQ(9)
     67#define ETHERNET_IRQ		SYSINT2_IRQ(10)
     68#define SYSINT2_IRQ_LAST	ETHERNET_IRQ
     69
     70/*
     71 * GIU Interrupt Numbers
     72 */
     73#define GIU_IRQ_BASE		40
     74#define GIU_IRQ(x)		(GIU_IRQ_BASE + (x))	/* IRQ 40-71 */
     75#define GIU_IRQ_LAST		GIU_IRQ(31)
     76
     77/*
     78 * VRC4173 Interrupt Numbers
     79 */
     80#define VRC4173_IRQ_BASE	72
     81#define VRC4173_IRQ(x)		(VRC4173_IRQ_BASE + (x))
     82#define VRC4173_USB_IRQ		VRC4173_IRQ(0)
     83#define VRC4173_PCMCIA2_IRQ	VRC4173_IRQ(1)
     84#define VRC4173_PCMCIA1_IRQ	VRC4173_IRQ(2)
     85#define VRC4173_PS2CH2_IRQ	VRC4173_IRQ(3)
     86#define VRC4173_PS2CH1_IRQ	VRC4173_IRQ(4)
     87#define VRC4173_PIU_IRQ		VRC4173_IRQ(5)
     88#define VRC4173_AIU_IRQ		VRC4173_IRQ(6)
     89#define VRC4173_KIU_IRQ		VRC4173_IRQ(7)
     90#define VRC4173_GIU_IRQ		VRC4173_IRQ(8)
     91#define VRC4173_AC97_IRQ	VRC4173_IRQ(9)
     92#define VRC4173_AC97INT1_IRQ	VRC4173_IRQ(10)
     93/* RFU */
     94#define VRC4173_DOZEPIU_IRQ	VRC4173_IRQ(13)
     95#define VRC4173_IRQ_LAST	VRC4173_DOZEPIU_IRQ
     96
     97#endif /* __NEC_VR41XX_IRQ_H */