cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sysctrl.c (18161B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 *
      4 *  Copyright (C) 2011-2012 John Crispin <john@phrozen.org>
      5 *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
      6 */
      7
      8#include <linux/ioport.h>
      9#include <linux/export.h>
     10#include <linux/clkdev.h>
     11#include <linux/spinlock.h>
     12#include <linux/of.h>
     13#include <linux/of_platform.h>
     14#include <linux/of_address.h>
     15
     16#include <lantiq_soc.h>
     17
     18#include "../clk.h"
     19#include "../prom.h"
     20
     21/* clock control register for legacy */
     22#define CGU_IFCCR	0x0018
     23#define CGU_IFCCR_VR9	0x0024
     24/* system clock register for legacy */
     25#define CGU_SYS		0x0010
     26/* pci control register */
     27#define CGU_PCICR	0x0034
     28#define CGU_PCICR_VR9	0x0038
     29/* ephy configuration register */
     30#define CGU_EPHY	0x10
     31
     32/* Legacy PMU register for ar9, ase, danube */
     33/* power control register */
     34#define PMU_PWDCR	0x1C
     35/* power status register */
     36#define PMU_PWDSR	0x20
     37/* power control register */
     38#define PMU_PWDCR1	0x24
     39/* power status register */
     40#define PMU_PWDSR1	0x28
     41/* power control register */
     42#define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
     43/* power status register */
     44#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
     45
     46
     47/* PMU register for ar10 and grx390 */
     48
     49/* First register set */
     50#define PMU_CLK_SR	0x20 /* status */
     51#define PMU_CLK_CR_A	0x24 /* Enable */
     52#define PMU_CLK_CR_B	0x28 /* Disable */
     53/* Second register set */
     54#define PMU_CLK_SR1	0x30 /* status */
     55#define PMU_CLK_CR1_A	0x34 /* Enable */
     56#define PMU_CLK_CR1_B	0x38 /* Disable */
     57/* Third register set */
     58#define PMU_ANA_SR	0x40 /* status */
     59#define PMU_ANA_CR_A	0x44 /* Enable */
     60#define PMU_ANA_CR_B	0x48 /* Disable */
     61
     62/* Status */
     63static u32 pmu_clk_sr[] = {
     64	PMU_CLK_SR,
     65	PMU_CLK_SR1,
     66	PMU_ANA_SR,
     67};
     68
     69/* Enable */
     70static u32 pmu_clk_cr_a[] = {
     71	PMU_CLK_CR_A,
     72	PMU_CLK_CR1_A,
     73	PMU_ANA_CR_A,
     74};
     75
     76/* Disable */
     77static u32 pmu_clk_cr_b[] = {
     78	PMU_CLK_CR_B,
     79	PMU_CLK_CR1_B,
     80	PMU_ANA_CR_B,
     81};
     82
     83#define PWDCR_EN_XRX(x)		(pmu_clk_cr_a[(x)])
     84#define PWDCR_DIS_XRX(x)	(pmu_clk_cr_b[(x)])
     85#define PWDSR_XRX(x)		(pmu_clk_sr[(x)])
     86
     87/* clock gates that we can en/disable */
     88#define PMU_USB0_P	BIT(0)
     89#define PMU_ASE_SDIO	BIT(2) /* ASE special */
     90#define PMU_PCI		BIT(4)
     91#define PMU_DMA		BIT(5)
     92#define PMU_USB0	BIT(6)
     93#define PMU_ASC0	BIT(7)
     94#define PMU_EPHY	BIT(7)	/* ase */
     95#define PMU_USIF	BIT(7) /* from vr9 until grx390 */
     96#define PMU_SPI		BIT(8)
     97#define PMU_DFE		BIT(9)
     98#define PMU_EBU		BIT(10)
     99#define PMU_STP		BIT(11)
    100#define PMU_GPT		BIT(12)
    101#define PMU_AHBS	BIT(13) /* vr9 */
    102#define PMU_FPI		BIT(14)
    103#define PMU_AHBM	BIT(15)
    104#define PMU_SDIO	BIT(16) /* danube, ar9, vr9 */
    105#define PMU_ASC1	BIT(17)
    106#define PMU_PPE_QSB	BIT(18)
    107#define PMU_PPE_SLL01	BIT(19)
    108#define PMU_DEU		BIT(20)
    109#define PMU_PPE_TC	BIT(21)
    110#define PMU_PPE_EMA	BIT(22)
    111#define PMU_PPE_DPLUM	BIT(23)
    112#define PMU_PPE_DP	BIT(23)
    113#define PMU_PPE_DPLUS	BIT(24)
    114#define PMU_USB1_P	BIT(26)
    115#define PMU_GPHY3	BIT(26) /* grx390 */
    116#define PMU_USB1	BIT(27)
    117#define PMU_SWITCH	BIT(28)
    118#define PMU_PPE_TOP	BIT(29)
    119#define PMU_GPHY0	BIT(29) /* ar10, xrx390 */
    120#define PMU_GPHY	BIT(30)
    121#define PMU_GPHY1	BIT(30) /* ar10, xrx390 */
    122#define PMU_PCIE_CLK	BIT(31)
    123#define PMU_GPHY2	BIT(31) /* ar10, xrx390 */
    124
    125#define PMU1_PCIE_PHY	BIT(0)	/* vr9-specific,moved in ar10/grx390 */
    126#define PMU1_PCIE_CTL	BIT(1)
    127#define PMU1_PCIE_PDI	BIT(4)
    128#define PMU1_PCIE_MSI	BIT(5)
    129#define PMU1_CKE	BIT(6)
    130#define PMU1_PCIE1_CTL	BIT(17)
    131#define PMU1_PCIE1_PDI	BIT(20)
    132#define PMU1_PCIE1_MSI	BIT(21)
    133#define PMU1_PCIE2_CTL	BIT(25)
    134#define PMU1_PCIE2_PDI	BIT(26)
    135#define PMU1_PCIE2_MSI	BIT(27)
    136
    137#define PMU_ANALOG_USB0_P	BIT(0)
    138#define PMU_ANALOG_USB1_P	BIT(1)
    139#define PMU_ANALOG_PCIE0_P	BIT(8)
    140#define PMU_ANALOG_PCIE1_P	BIT(9)
    141#define PMU_ANALOG_PCIE2_P	BIT(10)
    142#define PMU_ANALOG_DSL_AFE	BIT(16)
    143#define PMU_ANALOG_DCDC_2V5	BIT(17)
    144#define PMU_ANALOG_DCDC_1VX	BIT(18)
    145#define PMU_ANALOG_DCDC_1V0	BIT(19)
    146
    147#define pmu_w32(x, y)	ltq_w32((x), pmu_membase + (y))
    148#define pmu_r32(x)	ltq_r32(pmu_membase + (x))
    149
    150static void __iomem *pmu_membase;
    151void __iomem *ltq_cgu_membase;
    152void __iomem *ltq_ebu_membase;
    153
    154static u32 ifccr = CGU_IFCCR;
    155static u32 pcicr = CGU_PCICR;
    156
    157static DEFINE_SPINLOCK(g_pmu_lock);
    158
    159/* legacy function kept alive to ease clkdev transition */
    160void ltq_pmu_enable(unsigned int module)
    161{
    162	int retry = 1000000;
    163
    164	spin_lock(&g_pmu_lock);
    165	pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
    166	do {} while (--retry && (pmu_r32(PMU_PWDSR) & module));
    167	spin_unlock(&g_pmu_lock);
    168
    169	if (!retry)
    170		panic("activating PMU module failed!");
    171}
    172EXPORT_SYMBOL(ltq_pmu_enable);
    173
    174/* legacy function kept alive to ease clkdev transition */
    175void ltq_pmu_disable(unsigned int module)
    176{
    177	int retry = 1000000;
    178
    179	spin_lock(&g_pmu_lock);
    180	pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
    181	do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module)));
    182	spin_unlock(&g_pmu_lock);
    183
    184	if (!retry)
    185		pr_warn("deactivating PMU module failed!");
    186}
    187EXPORT_SYMBOL(ltq_pmu_disable);
    188
    189/* enable a hw clock */
    190static int cgu_enable(struct clk *clk)
    191{
    192	ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
    193	return 0;
    194}
    195
    196/* disable a hw clock */
    197static void cgu_disable(struct clk *clk)
    198{
    199	ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
    200}
    201
    202/* enable a clock gate */
    203static int pmu_enable(struct clk *clk)
    204{
    205	int retry = 1000000;
    206
    207	if (of_machine_is_compatible("lantiq,ar10")
    208	    || of_machine_is_compatible("lantiq,grx390")) {
    209		pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module));
    210		do {} while (--retry &&
    211			     (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)));
    212
    213	} else {
    214		spin_lock(&g_pmu_lock);
    215		pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
    216				PWDCR(clk->module));
    217		do {} while (--retry &&
    218			     (pmu_r32(PWDSR(clk->module)) & clk->bits));
    219		spin_unlock(&g_pmu_lock);
    220	}
    221
    222	if (!retry)
    223		panic("activating PMU module failed!");
    224
    225	return 0;
    226}
    227
    228/* disable a clock gate */
    229static void pmu_disable(struct clk *clk)
    230{
    231	int retry = 1000000;
    232
    233	if (of_machine_is_compatible("lantiq,ar10")
    234	    || of_machine_is_compatible("lantiq,grx390")) {
    235		pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module));
    236		do {} while (--retry &&
    237			     (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits));
    238	} else {
    239		spin_lock(&g_pmu_lock);
    240		pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
    241				PWDCR(clk->module));
    242		do {} while (--retry &&
    243			     (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
    244		spin_unlock(&g_pmu_lock);
    245	}
    246
    247	if (!retry)
    248		pr_warn("deactivating PMU module failed!");
    249}
    250
    251/* the pci enable helper */
    252static int pci_enable(struct clk *clk)
    253{
    254	unsigned int val = ltq_cgu_r32(ifccr);
    255	/* set bus clock speed */
    256	if (of_machine_is_compatible("lantiq,ar9") ||
    257			of_machine_is_compatible("lantiq,vr9")) {
    258		val &= ~0x1f00000;
    259		if (clk->rate == CLOCK_33M)
    260			val |= 0xe00000;
    261		else
    262			val |= 0x700000; /* 62.5M */
    263	} else {
    264		val &= ~0xf00000;
    265		if (clk->rate == CLOCK_33M)
    266			val |= 0x800000;
    267		else
    268			val |= 0x400000; /* 62.5M */
    269	}
    270	ltq_cgu_w32(val, ifccr);
    271	pmu_enable(clk);
    272	return 0;
    273}
    274
    275/* enable the external clock as a source */
    276static int pci_ext_enable(struct clk *clk)
    277{
    278	ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
    279	ltq_cgu_w32((1 << 30), pcicr);
    280	return 0;
    281}
    282
    283/* disable the external clock as a source */
    284static void pci_ext_disable(struct clk *clk)
    285{
    286	ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
    287	ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
    288}
    289
    290/* enable a clockout source */
    291static int clkout_enable(struct clk *clk)
    292{
    293	int i;
    294
    295	/* get the correct rate */
    296	for (i = 0; i < 4; i++) {
    297		if (clk->rates[i] == clk->rate) {
    298			int shift = 14 - (2 * clk->module);
    299			int enable = 7 - clk->module;
    300			unsigned int val = ltq_cgu_r32(ifccr);
    301
    302			val &= ~(3 << shift);
    303			val |= i << shift;
    304			val |= enable;
    305			ltq_cgu_w32(val, ifccr);
    306			return 0;
    307		}
    308	}
    309	return -1;
    310}
    311
    312/* manage the clock gates via PMU */
    313static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate,
    314			   unsigned int module, unsigned int bits)
    315{
    316	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
    317
    318	if (!clk)
    319		return;
    320	clk->cl.dev_id = dev;
    321	clk->cl.con_id = con;
    322	clk->cl.clk = clk;
    323	clk->enable = pmu_enable;
    324	clk->disable = pmu_disable;
    325	clk->module = module;
    326	clk->bits = bits;
    327	if (deactivate) {
    328		/*
    329		 * Disable it during the initialization. Module should enable
    330		 * when used
    331		 */
    332		pmu_disable(clk);
    333	}
    334	clkdev_add(&clk->cl);
    335}
    336
    337/* manage the clock generator */
    338static void clkdev_add_cgu(const char *dev, const char *con,
    339					unsigned int bits)
    340{
    341	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
    342
    343	if (!clk)
    344		return;
    345	clk->cl.dev_id = dev;
    346	clk->cl.con_id = con;
    347	clk->cl.clk = clk;
    348	clk->enable = cgu_enable;
    349	clk->disable = cgu_disable;
    350	clk->bits = bits;
    351	clkdev_add(&clk->cl);
    352}
    353
    354/* pci needs its own enable function as the setup is a bit more complex */
    355static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
    356
    357static void clkdev_add_pci(void)
    358{
    359	struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
    360	struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
    361
    362	/* main pci clock */
    363	if (clk) {
    364		clk->cl.dev_id = "17000000.pci";
    365		clk->cl.con_id = NULL;
    366		clk->cl.clk = clk;
    367		clk->rate = CLOCK_33M;
    368		clk->rates = valid_pci_rates;
    369		clk->enable = pci_enable;
    370		clk->disable = pmu_disable;
    371		clk->module = 0;
    372		clk->bits = PMU_PCI;
    373		clkdev_add(&clk->cl);
    374	}
    375
    376	/* use internal/external bus clock */
    377	if (clk_ext) {
    378		clk_ext->cl.dev_id = "17000000.pci";
    379		clk_ext->cl.con_id = "external";
    380		clk_ext->cl.clk = clk_ext;
    381		clk_ext->enable = pci_ext_enable;
    382		clk_ext->disable = pci_ext_disable;
    383		clkdev_add(&clk_ext->cl);
    384	}
    385}
    386
    387/* xway socs can generate clocks on gpio pins */
    388static unsigned long valid_clkout_rates[4][5] = {
    389	{CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
    390	{CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
    391	{CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
    392	{CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
    393};
    394
    395static void clkdev_add_clkout(void)
    396{
    397	int i;
    398
    399	for (i = 0; i < 4; i++) {
    400		struct clk *clk;
    401		char *name;
    402
    403		name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
    404		if (!name)
    405			continue;
    406		sprintf(name, "clkout%d", i);
    407
    408		clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
    409		if (!clk) {
    410			kfree(name);
    411			continue;
    412		}
    413		clk->cl.dev_id = "1f103000.cgu";
    414		clk->cl.con_id = name;
    415		clk->cl.clk = clk;
    416		clk->rate = 0;
    417		clk->rates = valid_clkout_rates[i];
    418		clk->enable = clkout_enable;
    419		clk->module = i;
    420		clkdev_add(&clk->cl);
    421	}
    422}
    423
    424/* bring up all register ranges that we need for basic system control */
    425void __init ltq_soc_init(void)
    426{
    427	struct resource res_pmu, res_cgu, res_ebu;
    428	struct device_node *np_pmu =
    429			of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
    430	struct device_node *np_cgu =
    431			of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
    432	struct device_node *np_ebu =
    433			of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
    434
    435	/* check if all the core register ranges are available */
    436	if (!np_pmu || !np_cgu || !np_ebu)
    437		panic("Failed to load core nodes from devicetree");
    438
    439	if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
    440			of_address_to_resource(np_cgu, 0, &res_cgu) ||
    441			of_address_to_resource(np_ebu, 0, &res_ebu))
    442		panic("Failed to get core resources");
    443
    444	of_node_put(np_pmu);
    445	of_node_put(np_cgu);
    446	of_node_put(np_ebu);
    447
    448	if (!request_mem_region(res_pmu.start, resource_size(&res_pmu),
    449				res_pmu.name) ||
    450		!request_mem_region(res_cgu.start, resource_size(&res_cgu),
    451				res_cgu.name) ||
    452		!request_mem_region(res_ebu.start, resource_size(&res_ebu),
    453				res_ebu.name))
    454		pr_err("Failed to request core resources");
    455
    456	pmu_membase = ioremap(res_pmu.start, resource_size(&res_pmu));
    457	ltq_cgu_membase = ioremap(res_cgu.start,
    458						resource_size(&res_cgu));
    459	ltq_ebu_membase = ioremap(res_ebu.start,
    460						resource_size(&res_ebu));
    461	if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
    462		panic("Failed to remap core resources");
    463
    464	/* make sure to unprotect the memory region where flash is located */
    465	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
    466
    467	/* add our generic xway clocks */
    468	clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
    469	clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
    470	clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
    471	clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
    472	clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
    473	clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
    474	clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
    475	clkdev_add_clkout();
    476
    477	/* add the soc dependent clocks */
    478	if (of_machine_is_compatible("lantiq,vr9")) {
    479		ifccr = CGU_IFCCR_VR9;
    480		pcicr = CGU_PCICR_VR9;
    481	} else {
    482		clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
    483	}
    484
    485	if (!of_machine_is_compatible("lantiq,ase"))
    486		clkdev_add_pci();
    487
    488	if (of_machine_is_compatible("lantiq,grx390") ||
    489	    of_machine_is_compatible("lantiq,ar10")) {
    490		clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY0);
    491		clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY1);
    492		clkdev_add_pmu("1e108000.switch", "gphy2", 0, 0, PMU_GPHY2);
    493		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P);
    494		clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P);
    495		/* rc 0 */
    496		clkdev_add_pmu("1f106800.phy", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
    497		clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
    498		clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
    499		clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
    500		/* rc 1 */
    501		clkdev_add_pmu("1f700400.phy", "phy", 1, 2, PMU_ANALOG_PCIE1_P);
    502		clkdev_add_pmu("19000000.pcie", "msi", 1, 1, PMU1_PCIE1_MSI);
    503		clkdev_add_pmu("1f700400.phy", "pdi", 1, 1, PMU1_PCIE1_PDI);
    504		clkdev_add_pmu("19000000.pcie", "ctl", 1, 1, PMU1_PCIE1_CTL);
    505	}
    506
    507	if (of_machine_is_compatible("lantiq,ase")) {
    508		if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
    509			clkdev_add_static(CLOCK_266M, CLOCK_133M,
    510						CLOCK_133M, CLOCK_266M);
    511		else
    512			clkdev_add_static(CLOCK_133M, CLOCK_133M,
    513						CLOCK_133M, CLOCK_133M);
    514		clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
    515		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
    516		clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
    517		clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
    518		clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
    519		clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO);
    520		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
    521	} else if (of_machine_is_compatible("lantiq,grx390")) {
    522		clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
    523				  ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
    524		clkdev_add_pmu("1e108000.switch", "gphy3", 0, 0, PMU_GPHY3);
    525		clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
    526		clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
    527		/* rc 2 */
    528		clkdev_add_pmu("1f106a00.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);
    529		clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
    530		clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
    531		clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
    532		clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
    533		clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
    534		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
    535	} else if (of_machine_is_compatible("lantiq,ar10")) {
    536		clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),
    537				  ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
    538		clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
    539		clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
    540		clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |
    541			       PMU_PPE_DP | PMU_PPE_TC);
    542		clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
    543		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
    544		clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
    545		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
    546	} else if (of_machine_is_compatible("lantiq,vr9")) {
    547		clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
    548				ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
    549		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
    550		clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
    551		clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
    552		clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
    553		clkdev_add_pmu("1f106800.phy", "phy", 1, 1, PMU1_PCIE_PHY);
    554		clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
    555		clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
    556		clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
    557		clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
    558		clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
    559
    560		clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
    561		clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,
    562				PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
    563				PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
    564				PMU_PPE_QSB | PMU_PPE_TOP);
    565		clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
    566		clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
    567		clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
    568		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
    569		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
    570	} else if (of_machine_is_compatible("lantiq,ar9")) {
    571		clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
    572				ltq_ar9_fpi_hz(), CLOCK_250M);
    573		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
    574		clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
    575		clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
    576		clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
    577		clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
    578		clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
    579		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
    580		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
    581		clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
    582	} else {
    583		clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
    584				ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
    585		clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
    586		clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
    587		clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
    588		clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
    589		clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
    590		clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
    591	}
    592}