cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cs5536_ohci.c (3761B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * the OHCI Virtual Support Module of AMD CS5536
      4 *
      5 * Copyright (C) 2007 Lemote, Inc.
      6 * Author : jlliu, liujl@lemote.com
      7 *
      8 * Copyright (C) 2009 Lemote, Inc.
      9 * Author: Wu Zhangjin, wuzhangjin@gmail.com
     10 */
     11
     12#include <cs5536/cs5536.h>
     13#include <cs5536/cs5536_pci.h>
     14
     15void pci_ohci_write_reg(int reg, u32 value)
     16{
     17	u32 hi = 0, lo = value;
     18
     19	switch (reg) {
     20	case PCI_COMMAND:
     21		_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
     22		if (value & PCI_COMMAND_MASTER)
     23			hi |= PCI_COMMAND_MASTER;
     24		else
     25			hi &= ~PCI_COMMAND_MASTER;
     26
     27		if (value & PCI_COMMAND_MEMORY)
     28			hi |= PCI_COMMAND_MEMORY;
     29		else
     30			hi &= ~PCI_COMMAND_MEMORY;
     31		_wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
     32		break;
     33	case PCI_STATUS:
     34		if (value & PCI_STATUS_PARITY) {
     35			_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
     36			if (lo & SB_PARE_ERR_FLAG) {
     37				lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG;
     38				_wrmsr(SB_MSR_REG(SB_ERROR), hi, lo);
     39			}
     40		}
     41		break;
     42	case PCI_BAR0_REG:
     43		if (value == PCI_BAR_RANGE_MASK) {
     44			_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
     45			lo |= SOFT_BAR_OHCI_FLAG;
     46			_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
     47		} else if ((value & 0x01) == 0x00) {
     48			_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
     49			lo = value;
     50			_wrmsr(USB_MSR_REG(USB_OHCI), hi, lo);
     51
     52			value &= 0xfffffff0;
     53			hi = 0x40000000 | ((value & 0xff000000) >> 24);
     54			lo = 0x000fffff | ((value & 0x00fff000) << 8);
     55			_wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo);
     56		}
     57		break;
     58	case PCI_OHCI_INT_REG:
     59		_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
     60		lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT);
     61		if (value)	/* enable all the usb interrupt in PIC */
     62			lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT);
     63		_wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo);
     64		break;
     65	default:
     66		break;
     67	}
     68}
     69
     70u32 pci_ohci_read_reg(int reg)
     71{
     72	u32 conf_data = 0;
     73	u32 hi, lo;
     74
     75	switch (reg) {
     76	case PCI_VENDOR_ID:
     77		conf_data =
     78		    CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID);
     79		break;
     80	case PCI_COMMAND:
     81		_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
     82		if (hi & PCI_COMMAND_MASTER)
     83			conf_data |= PCI_COMMAND_MASTER;
     84		if (hi & PCI_COMMAND_MEMORY)
     85			conf_data |= PCI_COMMAND_MEMORY;
     86		break;
     87	case PCI_STATUS:
     88		conf_data |= PCI_STATUS_66MHZ;
     89		conf_data |= PCI_STATUS_FAST_BACK;
     90		_rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo);
     91		if (lo & SB_PARE_ERR_FLAG)
     92			conf_data |= PCI_STATUS_PARITY;
     93		conf_data |= PCI_STATUS_DEVSEL_MEDIUM;
     94		break;
     95	case PCI_CLASS_REVISION:
     96		_rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo);
     97		conf_data = lo & 0x000000ff;
     98		conf_data |= (CS5536_OHCI_CLASS_CODE << 8);
     99		break;
    100	case PCI_CACHE_LINE_SIZE:
    101		conf_data =
    102		    CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE,
    103					    PCI_NORMAL_LATENCY_TIMER);
    104		break;
    105	case PCI_BAR0_REG:
    106		_rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo);
    107		if (lo & SOFT_BAR_OHCI_FLAG) {
    108			conf_data = CS5536_OHCI_RANGE |
    109			    PCI_BASE_ADDRESS_SPACE_MEMORY;
    110			lo &= ~SOFT_BAR_OHCI_FLAG;
    111			_wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo);
    112		} else {
    113			_rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo);
    114			conf_data = lo & 0xffffff00;
    115			conf_data &= ~0x0000000f;	/* 32bit mem */
    116		}
    117		break;
    118	case PCI_CARDBUS_CIS:
    119		conf_data = PCI_CARDBUS_CIS_POINTER;
    120		break;
    121	case PCI_SUBSYSTEM_VENDOR_ID:
    122		conf_data =
    123		    CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID);
    124		break;
    125	case PCI_ROM_ADDRESS:
    126		conf_data = PCI_EXPANSION_ROM_BAR;
    127		break;
    128	case PCI_CAPABILITY_LIST:
    129		conf_data = PCI_CAPLIST_USB_POINTER;
    130		break;
    131	case PCI_INTERRUPT_LINE:
    132		conf_data =
    133		    CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR);
    134		break;
    135	case PCI_OHCI_INT_REG:
    136		_rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo);
    137		if (((lo >> PIC_YSEL_LOW_USB_SHIFT) & 0xf) == CS5536_USB_INTR)
    138			conf_data = 1;
    139		break;
    140	default:
    141		break;
    142	}
    143
    144	return conf_data;
    145}