cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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init.c (1124B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright (C) 2009 Lemote Inc.
      4 * Author: Wu Zhangjin, wuzhangjin@gmail.com
      5 */
      6
      7#include <linux/memblock.h>
      8#include <asm/bootinfo.h>
      9#include <asm/traps.h>
     10#include <asm/smp-ops.h>
     11#include <asm/cacheflush.h>
     12#include <asm/fw/fw.h>
     13
     14#include <loongson.h>
     15
     16/* Loongson CPU address windows config space base address */
     17unsigned long __maybe_unused _loongson_addrwincfg_base;
     18
     19static void __init mips_nmi_setup(void)
     20{
     21	void *base;
     22
     23	base = (void *)(CAC_BASE + 0x380);
     24	memcpy(base, except_vec_nmi, 0x80);
     25	flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
     26}
     27
     28void __init prom_init(void)
     29{
     30#ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
     31	_loongson_addrwincfg_base = (unsigned long)
     32		ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE);
     33#endif
     34
     35	fw_init_cmdline();
     36	prom_init_machtype();
     37	prom_init_env();
     38
     39	/* init base address of io space */
     40	set_io_port_base((unsigned long)
     41		ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
     42	prom_init_memory();
     43
     44	/*init the uart base address */
     45	prom_init_uart_base();
     46	board_nmi_handler_setup = mips_nmi_setup;
     47}