cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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irq.c (3071B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright (C) 2007 Lemote Inc.
      4 * Author: Fuxin Zhang, zhangfx@lemote.com
      5 */
      6
      7#include <linux/export.h>
      8#include <linux/init.h>
      9#include <linux/interrupt.h>
     10
     11#include <asm/irq_cpu.h>
     12#include <asm/i8259.h>
     13#include <asm/mipsregs.h>
     14
     15#include <loongson.h>
     16#include <machine.h>
     17
     18#define LOONGSON_TIMER_IRQ	(MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
     19#define LOONGSON_NORTH_BRIDGE_IRQ	(MIPS_CPU_IRQ_BASE + 6) /* bonito */
     20#define LOONGSON_UART_IRQ	(MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
     21#define LOONGSON_SOUTH_BRIDGE_IRQ	(MIPS_CPU_IRQ_BASE + 2) /* i8259 */
     22
     23#define LOONGSON_INT_BIT_INT0		(1 << 11)
     24#define LOONGSON_INT_BIT_INT1		(1 << 12)
     25
     26/*
     27 * The generic i8259_irq() make the kernel hang on booting.  Since we cannot
     28 * get the irq via the IRR directly, we access the ISR instead.
     29 */
     30int mach_i8259_irq(void)
     31{
     32	int irq, isr;
     33
     34	irq = -1;
     35
     36	if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
     37		raw_spin_lock(&i8259A_lock);
     38		isr = inb(PIC_MASTER_CMD) &
     39			~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
     40		if (!isr)
     41			isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8;
     42		irq = ffs(isr) - 1;
     43		if (unlikely(irq == 7)) {
     44			/*
     45			 * This may be a spurious interrupt.
     46			 *
     47			 * Read the interrupt status register (ISR). If the most
     48			 * significant bit is not set then there is no valid
     49			 * interrupt.
     50			 */
     51			outb(0x0B, PIC_MASTER_ISR);	/* ISR register */
     52			if (~inb(PIC_MASTER_ISR) & 0x80)
     53				irq = -1;
     54		}
     55		raw_spin_unlock(&i8259A_lock);
     56	}
     57
     58	return irq;
     59}
     60EXPORT_SYMBOL(mach_i8259_irq);
     61
     62static void i8259_irqdispatch(void)
     63{
     64	int irq;
     65
     66	irq = mach_i8259_irq();
     67	if (irq >= 0)
     68		do_IRQ(irq);
     69	else
     70		spurious_interrupt();
     71}
     72
     73void mach_irq_dispatch(unsigned int pending)
     74{
     75	if (pending & CAUSEF_IP7)
     76		do_IRQ(LOONGSON_TIMER_IRQ);
     77	else if (pending & CAUSEF_IP6) {	/* North Bridge, Perf counter */
     78		bonito_irqdispatch();
     79	} else if (pending & CAUSEF_IP3)	/* CPU UART */
     80		do_IRQ(LOONGSON_UART_IRQ);
     81	else if (pending & CAUSEF_IP2)	/* South Bridge */
     82		i8259_irqdispatch();
     83	else
     84		spurious_interrupt();
     85}
     86
     87static irqreturn_t ip6_action(int cpl, void *dev_id)
     88{
     89	return IRQ_HANDLED;
     90}
     91
     92void __init mach_init_irq(void)
     93{
     94	/* init all controller
     95	 *   0-15	  ------> i8259 interrupt
     96	 *   16-23	  ------> mips cpu interrupt
     97	 *   32-63	  ------> bonito irq
     98	 */
     99
    100	/* setup cs5536 as high level trigger */
    101	LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
    102	LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
    103
    104	/* Sets the first-level interrupt dispatcher. */
    105	mips_cpu_irq_init();
    106	init_i8259_irqs();
    107	bonito_irq_init();
    108
    109	/* setup north bridge irq (bonito) */
    110	if (request_irq(LOONGSON_NORTH_BRIDGE_IRQ, ip6_action,
    111			IRQF_SHARED | IRQF_NO_THREAD, "cascade", ip6_action))
    112		pr_err("Failed to register north bridge cascade interrupt\n");
    113	/* setup source bridge irq (i8259) */
    114	if (request_irq(LOONGSON_SOUTH_BRIDGE_IRQ, no_action,
    115			IRQF_NO_THREAD | IRQF_NO_SUSPEND, "cascade", NULL))
    116		pr_err("Failed to register south bridge cascade interrupt\n");
    117}