cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pci-xtalk-bridge.c (20201B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Copyright (C) 2003 Christoph Hellwig (hch@lst.de)
      4 * Copyright (C) 1999, 2000, 04 Ralf Baechle (ralf@linux-mips.org)
      5 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
      6 */
      7#include <linux/kernel.h>
      8#include <linux/export.h>
      9#include <linux/pci.h>
     10#include <linux/smp.h>
     11#include <linux/dma-direct.h>
     12#include <linux/platform_device.h>
     13#include <linux/platform_data/xtalk-bridge.h>
     14#include <linux/nvmem-consumer.h>
     15#include <linux/crc16.h>
     16#include <linux/irqdomain.h>
     17
     18#include <asm/pci/bridge.h>
     19#include <asm/paccess.h>
     20#include <asm/sn/irq_alloc.h>
     21#include <asm/sn/ioc3.h>
     22
     23#define CRC16_INIT	0
     24#define CRC16_VALID	0xb001
     25
     26/*
     27 * Common phys<->dma mapping for platforms using pci xtalk bridge
     28 */
     29dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
     30{
     31	struct pci_dev *pdev = to_pci_dev(dev);
     32	struct bridge_controller *bc = BRIDGE_CONTROLLER(pdev->bus);
     33
     34	return bc->baddr + paddr;
     35}
     36
     37phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
     38{
     39	return dma_addr & ~(0xffUL << 56);
     40}
     41
     42/*
     43 * Most of the IOC3 PCI config register aren't present
     44 * we emulate what is needed for a normal PCI enumeration
     45 */
     46static int ioc3_cfg_rd(void *addr, int where, int size, u32 *value, u32 sid)
     47{
     48	u32 cf, shift, mask;
     49
     50	switch (where & ~3) {
     51	case 0x00 ... 0x10:
     52	case 0x40 ... 0x44:
     53		if (get_dbe(cf, (u32 *)addr))
     54			return PCIBIOS_DEVICE_NOT_FOUND;
     55		break;
     56	case 0x2c:
     57		cf = sid;
     58		break;
     59	case 0x3c:
     60		/* emulate sane interrupt pin value */
     61		cf = 0x00000100;
     62		break;
     63	default:
     64		cf = 0;
     65		break;
     66	}
     67	shift = (where & 3) << 3;
     68	mask = 0xffffffffU >> ((4 - size) << 3);
     69	*value = (cf >> shift) & mask;
     70
     71	return PCIBIOS_SUCCESSFUL;
     72}
     73
     74static int ioc3_cfg_wr(void *addr, int where, int size, u32 value)
     75{
     76	u32 cf, shift, mask, smask;
     77
     78	if ((where >= 0x14 && where < 0x40) || (where >= 0x48))
     79		return PCIBIOS_SUCCESSFUL;
     80
     81	if (get_dbe(cf, (u32 *)addr))
     82		return PCIBIOS_DEVICE_NOT_FOUND;
     83
     84	shift = ((where & 3) << 3);
     85	mask = (0xffffffffU >> ((4 - size) << 3));
     86	smask = mask << shift;
     87
     88	cf = (cf & ~smask) | ((value & mask) << shift);
     89	if (put_dbe(cf, (u32 *)addr))
     90		return PCIBIOS_DEVICE_NOT_FOUND;
     91
     92	return PCIBIOS_SUCCESSFUL;
     93}
     94
     95static void bridge_disable_swapping(struct pci_dev *dev)
     96{
     97	struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
     98	int slot = PCI_SLOT(dev->devfn);
     99
    100	/* Turn off byte swapping */
    101	bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
    102	bridge_read(bc, b_widget.w_tflush);	/* Flush */
    103}
    104
    105DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
    106	bridge_disable_swapping);
    107
    108
    109/*
    110 * The Bridge ASIC supports both type 0 and type 1 access.  Type 1 is
    111 * not really documented, so right now I can't write code which uses it.
    112 * Therefore we use type 0 accesses for now even though they won't work
    113 * correctly for PCI-to-PCI bridges.
    114 *
    115 * The function is complicated by the ultimate brokenness of the IOC3 chip
    116 * which is used in SGI systems.  The IOC3 can only handle 32-bit PCI
    117 * accesses and does only decode parts of it's address space.
    118 */
    119static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn,
    120				 int where, int size, u32 *value)
    121{
    122	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
    123	struct bridge_regs *bridge = bc->base;
    124	int slot = PCI_SLOT(devfn);
    125	int fn = PCI_FUNC(devfn);
    126	void *addr;
    127	u32 cf;
    128	int res;
    129
    130	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
    131	if (get_dbe(cf, (u32 *)addr))
    132		return PCIBIOS_DEVICE_NOT_FOUND;
    133
    134	/*
    135	 * IOC3 is broken beyond belief ...  Don't even give the
    136	 * generic PCI code a chance to look at it for real ...
    137	 */
    138	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
    139		addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
    140		return ioc3_cfg_rd(addr, where, size, value,
    141				   bc->ioc3_sid[slot]);
    142	}
    143
    144	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
    145
    146	if (size == 1)
    147		res = get_dbe(*value, (u8 *)addr);
    148	else if (size == 2)
    149		res = get_dbe(*value, (u16 *)addr);
    150	else
    151		res = get_dbe(*value, (u32 *)addr);
    152
    153	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
    154}
    155
    156static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn,
    157				 int where, int size, u32 *value)
    158{
    159	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
    160	struct bridge_regs *bridge = bc->base;
    161	int busno = bus->number;
    162	int slot = PCI_SLOT(devfn);
    163	int fn = PCI_FUNC(devfn);
    164	void *addr;
    165	u32 cf;
    166	int res;
    167
    168	bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
    169	addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
    170	if (get_dbe(cf, (u32 *)addr))
    171		return PCIBIOS_DEVICE_NOT_FOUND;
    172
    173	/*
    174	 * IOC3 is broken beyond belief ...  Don't even give the
    175	 * generic PCI code a chance to look at it for real ...
    176	 */
    177	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
    178		addr = &bridge->b_type1_cfg.c[(fn << 8) | (where & ~3)];
    179		return ioc3_cfg_rd(addr, where, size, value,
    180				   bc->ioc3_sid[slot]);
    181	}
    182
    183	addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
    184
    185	if (size == 1)
    186		res = get_dbe(*value, (u8 *)addr);
    187	else if (size == 2)
    188		res = get_dbe(*value, (u16 *)addr);
    189	else
    190		res = get_dbe(*value, (u32 *)addr);
    191
    192	return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
    193}
    194
    195static int pci_read_config(struct pci_bus *bus, unsigned int devfn,
    196			   int where, int size, u32 *value)
    197{
    198	if (!pci_is_root_bus(bus))
    199		return pci_conf1_read_config(bus, devfn, where, size, value);
    200
    201	return pci_conf0_read_config(bus, devfn, where, size, value);
    202}
    203
    204static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn,
    205				  int where, int size, u32 value)
    206{
    207	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
    208	struct bridge_regs *bridge = bc->base;
    209	int slot = PCI_SLOT(devfn);
    210	int fn = PCI_FUNC(devfn);
    211	void *addr;
    212	u32 cf;
    213	int res;
    214
    215	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID];
    216	if (get_dbe(cf, (u32 *)addr))
    217		return PCIBIOS_DEVICE_NOT_FOUND;
    218
    219	/*
    220	 * IOC3 is broken beyond belief ...  Don't even give the
    221	 * generic PCI code a chance to look at it for real ...
    222	 */
    223	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
    224		addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
    225		return ioc3_cfg_wr(addr, where, size, value);
    226	}
    227
    228	addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)];
    229
    230	if (size == 1)
    231		res = put_dbe(value, (u8 *)addr);
    232	else if (size == 2)
    233		res = put_dbe(value, (u16 *)addr);
    234	else
    235		res = put_dbe(value, (u32 *)addr);
    236
    237	if (res)
    238		return PCIBIOS_DEVICE_NOT_FOUND;
    239
    240	return PCIBIOS_SUCCESSFUL;
    241}
    242
    243static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn,
    244				  int where, int size, u32 value)
    245{
    246	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
    247	struct bridge_regs *bridge = bc->base;
    248	int slot = PCI_SLOT(devfn);
    249	int fn = PCI_FUNC(devfn);
    250	int busno = bus->number;
    251	void *addr;
    252	u32 cf;
    253	int res;
    254
    255	bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11));
    256	addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID];
    257	if (get_dbe(cf, (u32 *)addr))
    258		return PCIBIOS_DEVICE_NOT_FOUND;
    259
    260	/*
    261	 * IOC3 is broken beyond belief ...  Don't even give the
    262	 * generic PCI code a chance to look at it for real ...
    263	 */
    264	if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) {
    265		addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2];
    266		return ioc3_cfg_wr(addr, where, size, value);
    267	}
    268
    269	addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))];
    270
    271	if (size == 1)
    272		res = put_dbe(value, (u8 *)addr);
    273	else if (size == 2)
    274		res = put_dbe(value, (u16 *)addr);
    275	else
    276		res = put_dbe(value, (u32 *)addr);
    277
    278	if (res)
    279		return PCIBIOS_DEVICE_NOT_FOUND;
    280
    281	return PCIBIOS_SUCCESSFUL;
    282}
    283
    284static int pci_write_config(struct pci_bus *bus, unsigned int devfn,
    285	int where, int size, u32 value)
    286{
    287	if (!pci_is_root_bus(bus))
    288		return pci_conf1_write_config(bus, devfn, where, size, value);
    289
    290	return pci_conf0_write_config(bus, devfn, where, size, value);
    291}
    292
    293static struct pci_ops bridge_pci_ops = {
    294	.read	 = pci_read_config,
    295	.write	 = pci_write_config,
    296};
    297
    298struct bridge_irq_chip_data {
    299	struct bridge_controller *bc;
    300	nasid_t nasid;
    301};
    302
    303static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask,
    304			       bool force)
    305{
    306#ifdef CONFIG_NUMA
    307	struct bridge_irq_chip_data *data = d->chip_data;
    308	int bit = d->parent_data->hwirq;
    309	int pin = d->hwirq;
    310	int ret, cpu;
    311
    312	ret = irq_chip_set_affinity_parent(d, mask, force);
    313	if (ret >= 0) {
    314		cpu = cpumask_first_and(mask, cpu_online_mask);
    315		data->nasid = cpu_to_node(cpu);
    316		bridge_write(data->bc, b_int_addr[pin].addr,
    317			     (((data->bc->intr_addr >> 30) & 0x30000) |
    318			      bit | (data->nasid << 8)));
    319		bridge_read(data->bc, b_wid_tflush);
    320	}
    321	return ret;
    322#else
    323	return irq_chip_set_affinity_parent(d, mask, force);
    324#endif
    325}
    326
    327struct irq_chip bridge_irq_chip = {
    328	.name             = "BRIDGE",
    329	.irq_mask         = irq_chip_mask_parent,
    330	.irq_unmask       = irq_chip_unmask_parent,
    331	.irq_set_affinity = bridge_set_affinity
    332};
    333
    334static int bridge_domain_alloc(struct irq_domain *domain, unsigned int virq,
    335			       unsigned int nr_irqs, void *arg)
    336{
    337	struct bridge_irq_chip_data *data;
    338	struct irq_alloc_info *info = arg;
    339	int ret;
    340
    341	if (nr_irqs > 1 || !info)
    342		return -EINVAL;
    343
    344	data = kzalloc(sizeof(*data), GFP_KERNEL);
    345	if (!data)
    346		return -ENOMEM;
    347
    348	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
    349	if (ret >= 0) {
    350		data->bc = info->ctrl;
    351		data->nasid = info->nasid;
    352		irq_domain_set_info(domain, virq, info->pin, &bridge_irq_chip,
    353				    data, handle_level_irq, NULL, NULL);
    354	} else {
    355		kfree(data);
    356	}
    357
    358	return ret;
    359}
    360
    361static void bridge_domain_free(struct irq_domain *domain, unsigned int virq,
    362			       unsigned int nr_irqs)
    363{
    364	struct irq_data *irqd = irq_domain_get_irq_data(domain, virq);
    365
    366	if (nr_irqs)
    367		return;
    368
    369	kfree(irqd->chip_data);
    370	irq_domain_free_irqs_top(domain, virq, nr_irqs);
    371}
    372
    373static int bridge_domain_activate(struct irq_domain *domain,
    374				  struct irq_data *irqd, bool reserve)
    375{
    376	struct bridge_irq_chip_data *data = irqd->chip_data;
    377	struct bridge_controller *bc = data->bc;
    378	int bit = irqd->parent_data->hwirq;
    379	int pin = irqd->hwirq;
    380	u32 device;
    381
    382	bridge_write(bc, b_int_addr[pin].addr,
    383		     (((bc->intr_addr >> 30) & 0x30000) |
    384		      bit | (data->nasid << 8)));
    385	bridge_set(bc, b_int_enable, (1 << pin));
    386	bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */
    387
    388	/*
    389	 * Enable sending of an interrupt clear packet to the hub on a high to
    390	 * low transition of the interrupt pin.
    391	 *
    392	 * IRIX sets additional bits in the address which are documented as
    393	 * reserved in the bridge docs.
    394	 */
    395	bridge_set(bc, b_int_mode, (1UL << pin));
    396
    397	/*
    398	 * We assume the bridge to have a 1:1 mapping between devices
    399	 * (slots) and intr pins.
    400	 */
    401	device = bridge_read(bc, b_int_device);
    402	device &= ~(7 << (pin*3));
    403	device |= (pin << (pin*3));
    404	bridge_write(bc, b_int_device, device);
    405
    406	bridge_read(bc, b_wid_tflush);
    407	return 0;
    408}
    409
    410static void bridge_domain_deactivate(struct irq_domain *domain,
    411				     struct irq_data *irqd)
    412{
    413	struct bridge_irq_chip_data *data = irqd->chip_data;
    414
    415	bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq));
    416	bridge_read(data->bc, b_wid_tflush);
    417}
    418
    419static const struct irq_domain_ops bridge_domain_ops = {
    420	.alloc      = bridge_domain_alloc,
    421	.free       = bridge_domain_free,
    422	.activate   = bridge_domain_activate,
    423	.deactivate = bridge_domain_deactivate
    424};
    425
    426/*
    427 * All observed requests have pin == 1. We could have a global here, that
    428 * gets incremented and returned every time - unfortunately, pci_map_irq
    429 * may be called on the same device over and over, and need to return the
    430 * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
    431 *
    432 * A given PCI device, in general, should be able to intr any of the cpus
    433 * on any one of the hubs connected to its xbow.
    434 */
    435static int bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
    436{
    437	struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus);
    438	struct irq_alloc_info info;
    439	int irq;
    440
    441	switch (pin) {
    442	case PCI_INTERRUPT_UNKNOWN:
    443	case PCI_INTERRUPT_INTA:
    444	case PCI_INTERRUPT_INTC:
    445		pin = 0;
    446		break;
    447	case PCI_INTERRUPT_INTB:
    448	case PCI_INTERRUPT_INTD:
    449		pin = 1;
    450	}
    451
    452	irq = bc->pci_int[slot][pin];
    453	if (irq == -1) {
    454		info.ctrl = bc;
    455		info.nasid = bc->nasid;
    456		info.pin = bc->int_mapping[slot][pin];
    457
    458		irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info);
    459		if (irq < 0)
    460			return irq;
    461
    462		bc->pci_int[slot][pin] = irq;
    463	}
    464	return irq;
    465}
    466
    467#define IOC3_SID(sid)	(PCI_VENDOR_ID_SGI | ((sid) << 16))
    468
    469static void bridge_setup_ip27_baseio6g(struct bridge_controller *bc)
    470{
    471	bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO6G);
    472	bc->ioc3_sid[6] = IOC3_SID(IOC3_SUBSYS_IP27_MIO);
    473	bc->int_mapping[2][1] = 4;
    474	bc->int_mapping[6][1] = 6;
    475}
    476
    477static void bridge_setup_ip27_baseio(struct bridge_controller *bc)
    478{
    479	bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO);
    480	bc->int_mapping[2][1] = 4;
    481}
    482
    483static void bridge_setup_ip29_baseio(struct bridge_controller *bc)
    484{
    485	bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP29_SYSBOARD);
    486	bc->int_mapping[2][1] = 3;
    487}
    488
    489static void bridge_setup_ip30_sysboard(struct bridge_controller *bc)
    490{
    491	bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP30_SYSBOARD);
    492	bc->int_mapping[2][1] = 4;
    493}
    494
    495static void bridge_setup_menet(struct bridge_controller *bc)
    496{
    497	bc->ioc3_sid[0] = IOC3_SID(IOC3_SUBSYS_MENET);
    498	bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_MENET);
    499	bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_MENET);
    500	bc->ioc3_sid[3] = IOC3_SID(IOC3_SUBSYS_MENET4);
    501}
    502
    503static void bridge_setup_io7(struct bridge_controller *bc)
    504{
    505	bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO7);
    506}
    507
    508static void bridge_setup_io8(struct bridge_controller *bc)
    509{
    510	bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO8);
    511}
    512
    513static void bridge_setup_io9(struct bridge_controller *bc)
    514{
    515	bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_IO9);
    516}
    517
    518static void bridge_setup_ip34_fuel_sysboard(struct bridge_controller *bc)
    519{
    520	bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IP34_SYSBOARD);
    521}
    522
    523#define BRIDGE_BOARD_SETUP(_partno, _setup)	\
    524	{ .match = _partno, .setup = _setup }
    525
    526static const struct {
    527	char *match;
    528	void (*setup)(struct bridge_controller *bc);
    529} bridge_ioc3_devid[] = {
    530	BRIDGE_BOARD_SETUP("030-0734-", bridge_setup_ip27_baseio6g),
    531	BRIDGE_BOARD_SETUP("030-0880-", bridge_setup_ip27_baseio6g),
    532	BRIDGE_BOARD_SETUP("030-1023-", bridge_setup_ip27_baseio),
    533	BRIDGE_BOARD_SETUP("030-1124-", bridge_setup_ip27_baseio),
    534	BRIDGE_BOARD_SETUP("030-1025-", bridge_setup_ip29_baseio),
    535	BRIDGE_BOARD_SETUP("030-1244-", bridge_setup_ip29_baseio),
    536	BRIDGE_BOARD_SETUP("030-1389-", bridge_setup_ip29_baseio),
    537	BRIDGE_BOARD_SETUP("030-0887-", bridge_setup_ip30_sysboard),
    538	BRIDGE_BOARD_SETUP("030-1467-", bridge_setup_ip30_sysboard),
    539	BRIDGE_BOARD_SETUP("030-0873-", bridge_setup_menet),
    540	BRIDGE_BOARD_SETUP("030-1557-", bridge_setup_io7),
    541	BRIDGE_BOARD_SETUP("030-1673-", bridge_setup_io8),
    542	BRIDGE_BOARD_SETUP("030-1771-", bridge_setup_io9),
    543	BRIDGE_BOARD_SETUP("030-1707-", bridge_setup_ip34_fuel_sysboard),
    544};
    545
    546static void bridge_setup_board(struct bridge_controller *bc, char *partnum)
    547{
    548	int i;
    549
    550	for (i = 0; i < ARRAY_SIZE(bridge_ioc3_devid); i++)
    551		if (!strncmp(partnum, bridge_ioc3_devid[i].match,
    552			     strlen(bridge_ioc3_devid[i].match))) {
    553			bridge_ioc3_devid[i].setup(bc);
    554		}
    555}
    556
    557static int bridge_nvmem_match(struct device *dev, const void *data)
    558{
    559	const char *name = dev_name(dev);
    560	const char *prefix = data;
    561
    562	if (strlen(name) < strlen(prefix))
    563		return 0;
    564
    565	return memcmp(prefix, dev_name(dev), strlen(prefix)) == 0;
    566}
    567
    568static int bridge_get_partnum(u64 baddr, char *partnum)
    569{
    570	struct nvmem_device *nvmem;
    571	char prefix[24];
    572	u8 prom[64];
    573	int i, j;
    574	int ret;
    575
    576	snprintf(prefix, sizeof(prefix), "bridge-%012llx-0b-", baddr);
    577
    578	nvmem = nvmem_device_find(prefix, bridge_nvmem_match);
    579	if (IS_ERR(nvmem))
    580		return PTR_ERR(nvmem);
    581
    582	ret = nvmem_device_read(nvmem, 0, 64, prom);
    583	nvmem_device_put(nvmem);
    584
    585	if (ret != 64)
    586		return ret;
    587
    588	if (crc16(CRC16_INIT, prom, 32) != CRC16_VALID ||
    589	    crc16(CRC16_INIT, prom + 32, 32) != CRC16_VALID)
    590		return -EINVAL;
    591
    592	/* Assemble part number */
    593	j = 0;
    594	for (i = 0; i < 19; i++)
    595		if (prom[i + 11] != ' ')
    596			partnum[j++] = prom[i + 11];
    597
    598	for (i = 0; i < 6; i++)
    599		if (prom[i + 32] != ' ')
    600			partnum[j++] = prom[i + 32];
    601
    602	partnum[j] = 0;
    603
    604	return 0;
    605}
    606
    607static int bridge_probe(struct platform_device *pdev)
    608{
    609	struct xtalk_bridge_platform_data *bd = dev_get_platdata(&pdev->dev);
    610	struct device *dev = &pdev->dev;
    611	struct bridge_controller *bc;
    612	struct pci_host_bridge *host;
    613	struct irq_domain *domain, *parent;
    614	struct fwnode_handle *fn;
    615	char partnum[26];
    616	int slot;
    617	int err;
    618
    619	/* get part number from one wire prom */
    620	if (bridge_get_partnum(virt_to_phys((void *)bd->bridge_addr), partnum))
    621		return -EPROBE_DEFER; /* not available yet */
    622
    623	parent = irq_get_default_host();
    624	if (!parent)
    625		return -ENODEV;
    626	fn = irq_domain_alloc_named_fwnode("BRIDGE");
    627	if (!fn)
    628		return -ENOMEM;
    629	domain = irq_domain_create_hierarchy(parent, 0, 8, fn,
    630					     &bridge_domain_ops, NULL);
    631	if (!domain) {
    632		irq_domain_free_fwnode(fn);
    633		return -ENOMEM;
    634	}
    635
    636	pci_set_flags(PCI_PROBE_ONLY);
    637
    638	host = devm_pci_alloc_host_bridge(dev, sizeof(*bc));
    639	if (!host) {
    640		err = -ENOMEM;
    641		goto err_remove_domain;
    642	}
    643
    644	bc = pci_host_bridge_priv(host);
    645
    646	bc->busn.name		= "Bridge PCI busn";
    647	bc->busn.start		= 0;
    648	bc->busn.end		= 0xff;
    649	bc->busn.flags		= IORESOURCE_BUS;
    650
    651	bc->domain		= domain;
    652
    653	pci_add_resource_offset(&host->windows, &bd->mem, bd->mem_offset);
    654	pci_add_resource_offset(&host->windows, &bd->io, bd->io_offset);
    655	pci_add_resource(&host->windows, &bc->busn);
    656
    657	err = devm_request_pci_bus_resources(dev, &host->windows);
    658	if (err < 0)
    659		goto err_free_resource;
    660
    661	bc->nasid = bd->nasid;
    662
    663	bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR;
    664	bc->base = (struct bridge_regs *)bd->bridge_addr;
    665	bc->intr_addr = bd->intr_addr;
    666
    667	/*
    668	 * Clear all pending interrupts.
    669	 */
    670	bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR);
    671
    672	/*
    673	 * Until otherwise set up, assume all interrupts are from slot 0
    674	 */
    675	bridge_write(bc, b_int_device, 0x0);
    676
    677	/*
    678	 * disable swapping for big windows
    679	 */
    680	bridge_clr(bc, b_wid_control,
    681		   BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP);
    682#ifdef CONFIG_PAGE_SIZE_4KB
    683	bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
    684#else /* 16kB or larger */
    685	bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE);
    686#endif
    687
    688	/*
    689	 * Hmm...  IRIX sets additional bits in the address which
    690	 * are documented as reserved in the bridge docs.
    691	 */
    692	bridge_write(bc, b_wid_int_upper,
    693		     ((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16));
    694	bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff);
    695	bridge_write(bc, b_dir_map, (bd->masterwid << 20));	/* DMA */
    696	bridge_write(bc, b_int_enable, 0);
    697
    698	for (slot = 0; slot < 8; slot++) {
    699		bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR);
    700		bc->pci_int[slot][0] = -1;
    701		bc->pci_int[slot][1] = -1;
    702		/* default interrupt pin mapping */
    703		bc->int_mapping[slot][0] = slot;
    704		bc->int_mapping[slot][1] = slot ^ 4;
    705	}
    706	bridge_read(bc, b_wid_tflush);	  /* wait until Bridge PIO complete */
    707
    708	bridge_setup_board(bc, partnum);
    709
    710	host->dev.parent = dev;
    711	host->sysdata = bc;
    712	host->busnr = 0;
    713	host->ops = &bridge_pci_ops;
    714	host->map_irq = bridge_map_irq;
    715	host->swizzle_irq = pci_common_swizzle;
    716
    717	err = pci_scan_root_bus_bridge(host);
    718	if (err < 0)
    719		goto err_free_resource;
    720
    721	pci_bus_claim_resources(host->bus);
    722	pci_bus_add_devices(host->bus);
    723
    724	platform_set_drvdata(pdev, host->bus);
    725
    726	return 0;
    727
    728err_free_resource:
    729	pci_free_resource_list(&host->windows);
    730err_remove_domain:
    731	irq_domain_remove(domain);
    732	irq_domain_free_fwnode(fn);
    733	return err;
    734}
    735
    736static int bridge_remove(struct platform_device *pdev)
    737{
    738	struct pci_bus *bus = platform_get_drvdata(pdev);
    739	struct bridge_controller *bc = BRIDGE_CONTROLLER(bus);
    740	struct fwnode_handle *fn = bc->domain->fwnode;
    741
    742	irq_domain_remove(bc->domain);
    743	irq_domain_free_fwnode(fn);
    744	pci_lock_rescan_remove();
    745	pci_stop_root_bus(bus);
    746	pci_remove_root_bus(bus);
    747	pci_unlock_rescan_remove();
    748
    749	return 0;
    750}
    751
    752static struct platform_driver bridge_driver = {
    753	.probe  = bridge_probe,
    754	.remove = bridge_remove,
    755	.driver = {
    756		.name = "xtalk-bridge",
    757	}
    758};
    759
    760builtin_platform_driver(bridge_driver);