cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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setup.c (2803B)

      1// SPDX-License-Identifier: GPL-2.0-or-later
      2/*
      3 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
      4 */
      5#include <linux/init.h>
      6#include <linux/kernel.h>
      7#include <linux/export.h>
      8#include <linux/reboot.h>
      9#include <linux/string.h>
     10
     11#include <asm/bootinfo.h>
     12#include <asm/cpu.h>
     13#include <asm/mipsregs.h>
     14#include <asm/io.h>
     15#include <asm/sibyte/sb1250.h>
     16
     17#include <asm/sibyte/bcm1480_regs.h>
     18#include <asm/sibyte/bcm1480_scd.h>
     19#include <asm/sibyte/sb1250_scd.h>
     20
     21unsigned int sb1_pass;
     22unsigned int soc_pass;
     23unsigned int soc_type;
     24EXPORT_SYMBOL(soc_type);
     25unsigned int periph_rev;
     26EXPORT_SYMBOL_GPL(periph_rev);
     27unsigned int zbbus_mhz;
     28EXPORT_SYMBOL(zbbus_mhz);
     29
     30static unsigned int part_type;
     31
     32static char *soc_str;
     33static char *pass_str;
     34
     35static int __init setup_bcm1x80_bcm1x55(void)
     36{
     37	switch (soc_pass) {
     38	case K_SYS_REVISION_BCM1480_S0:
     39		periph_rev = 1;
     40		pass_str = "S0 (pass1)";
     41		break;
     42	case K_SYS_REVISION_BCM1480_A1:
     43		periph_rev = 1;
     44		pass_str = "A1 (pass1)";
     45		break;
     46	case K_SYS_REVISION_BCM1480_A2:
     47		periph_rev = 1;
     48		pass_str = "A2 (pass1)";
     49		break;
     50	case K_SYS_REVISION_BCM1480_A3:
     51		periph_rev = 1;
     52		pass_str = "A3 (pass1)";
     53		break;
     54	case K_SYS_REVISION_BCM1480_B0:
     55		periph_rev = 1;
     56		pass_str = "B0 (pass2)";
     57		break;
     58	default:
     59		printk("Unknown %s rev %x\n", soc_str, soc_pass);
     60		periph_rev = 1;
     61		pass_str = "Unknown Revision";
     62		break;
     63	}
     64
     65	return 0;
     66}
     67
     68/* Setup code likely to be common to all SiByte platforms */
     69
     70static int __init sys_rev_decode(void)
     71{
     72	int ret = 0;
     73
     74	switch (soc_type) {
     75	case K_SYS_SOC_TYPE_BCM1x80:
     76		if (part_type == K_SYS_PART_BCM1480)
     77		    soc_str = "BCM1480";
     78		else if (part_type == K_SYS_PART_BCM1280)
     79		    soc_str = "BCM1280";
     80		else
     81		    soc_str = "BCM1x80";
     82		ret = setup_bcm1x80_bcm1x55();
     83		break;
     84
     85	case K_SYS_SOC_TYPE_BCM1x55:
     86		if (part_type == K_SYS_PART_BCM1455)
     87		    soc_str = "BCM1455";
     88		else if (part_type == K_SYS_PART_BCM1255)
     89		    soc_str = "BCM1255";
     90		else
     91		    soc_str = "BCM1x55";
     92		ret = setup_bcm1x80_bcm1x55();
     93		break;
     94
     95	default:
     96		printk("Unknown part type %x\n", part_type);
     97		ret = 1;
     98		break;
     99	}
    100
    101	return ret;
    102}
    103
    104void __init bcm1480_setup(void)
    105{
    106	uint64_t sys_rev;
    107	int plldiv;
    108
    109	sb1_pass = read_c0_prid() & PRID_REV_MASK;
    110	sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
    111	soc_type = SYS_SOC_TYPE(sys_rev);
    112	part_type = G_SYS_PART(sys_rev);
    113	soc_pass = G_SYS_REVISION(sys_rev);
    114
    115	if (sys_rev_decode()) {
    116		printk("Restart after failure to identify SiByte chip\n");
    117		machine_restart(NULL);
    118	}
    119
    120	plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
    121	zbbus_mhz = ((plldiv >> 1) * 50) + ((plldiv & 1) * 25);
    122
    123	printk("Broadcom SiByte %s %s @ %d MHz (SB-1A rev %d)\n",
    124		    soc_str, pass_str, zbbus_mhz * 2, sb1_pass);
    125	printk("Board type: %s\n", get_system_type());
    126}