cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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irq_tx4927.c (1919B)


      1/*
      2 * Common tx4927 irq handler
      3 *
      4 * Author: MontaVista Software, Inc.
      5 *	   source@mvista.com
      6 *
      7 *  under the terms of the GNU General Public License as published by the
      8 *  Free Software Foundation; either version 2 of the License, or (at your
      9 *  option) any later version.
     10 *
     11 *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
     12 *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     13 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     14 *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     15 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     16 *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
     17 *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     18 *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
     19 *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
     20 *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     21 *
     22 *  You should have received a copy of the GNU General Public License along
     23 *  with this program; if not, write to the Free Software Foundation, Inc.,
     24 *  675 Mass Ave, Cambridge, MA 02139, USA.
     25 */
     26#include <linux/init.h>
     27#include <linux/interrupt.h>
     28#include <linux/irq.h>
     29#include <asm/irq_cpu.h>
     30#include <asm/txx9/tx4927.h>
     31
     32void __init tx4927_irq_init(void)
     33{
     34	int i;
     35
     36	mips_cpu_irq_init();
     37	txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
     38	irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
     39				handle_simple_irq);
     40	/* raise priority for errors, timers, SIO */
     41	txx9_irq_set_pri(TX4927_IR_ECCERR, 7);
     42	txx9_irq_set_pri(TX4927_IR_WTOERR, 7);
     43	txx9_irq_set_pri(TX4927_IR_PCIERR, 7);
     44	txx9_irq_set_pri(TX4927_IR_PCIPME, 7);
     45	for (i = 0; i < TX4927_NUM_IR_TMR; i++)
     46		txx9_irq_set_pri(TX4927_IR_TMR(i), 6);
     47	for (i = 0; i < TX4927_NUM_IR_SIO; i++)
     48		txx9_irq_set_pri(TX4927_IR_SIO(i), 5);
     49}