cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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elf.h (2675B)

      1/* SPDX-License-Identifier: GPL-2.0-or-later */
      2/*
      3 * Copyright (C) 2011 Tobias Klauser <tklauser@distanz.ch>
      4 */
      5
      6#ifndef _ASM_NIOS2_ELF_H
      7#define _ASM_NIOS2_ELF_H
      8
      9#include <uapi/asm/elf.h>
     10
     11/*
     12 * This is used to ensure we don't load something for the wrong architecture.
     13 */
     14#define elf_check_arch(x) ((x)->e_machine == EM_ALTERA_NIOS2)
     15
     16#define ELF_PLAT_INIT(_r, load_addr)
     17
     18#define CORE_DUMP_USE_REGSET
     19#define ELF_EXEC_PAGESIZE	4096
     20
     21/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
     22   use of this is to invoke "./ld.so someprog" to test out a new version of
     23   the loader.  We need to make sure that it is out of the way of the program
     24   that it will "exec", and that there is sufficient room for the brk.  */
     25
     26#define ELF_ET_DYN_BASE		0xD0000000UL
     27
     28/* regs is struct pt_regs, pr_reg is elf_gregset_t (which is
     29   now struct_user_regs, they are different) */
     30
     31#define ARCH_HAS_SETUP_ADDITIONAL_PAGES	1
     32struct linux_binprm;
     33extern int arch_setup_additional_pages(struct linux_binprm *bprm,
     34	int uses_interp);
     35#define ELF_CORE_COPY_REGS(pr_reg, regs)				\
     36{ do {									\
     37	/* Bleech. */							\
     38	pr_reg[0]  = regs->r8;						\
     39	pr_reg[1]  = regs->r9;						\
     40	pr_reg[2]  = regs->r10;						\
     41	pr_reg[3]  = regs->r11;						\
     42	pr_reg[4]  = regs->r12;						\
     43	pr_reg[5]  = regs->r13;						\
     44	pr_reg[6]  = regs->r14;						\
     45	pr_reg[7]  = regs->r15;						\
     46	pr_reg[8]  = regs->r1;						\
     47	pr_reg[9]  = regs->r2;						\
     48	pr_reg[10] = regs->r3;						\
     49	pr_reg[11] = regs->r4;						\
     50	pr_reg[12] = regs->r5;						\
     51	pr_reg[13] = regs->r6;						\
     52	pr_reg[14] = regs->r7;						\
     53	pr_reg[15] = regs->orig_r2;					\
     54	pr_reg[16] = regs->ra;						\
     55	pr_reg[17] = regs->fp;						\
     56	pr_reg[18] = regs->sp;						\
     57	pr_reg[19] = regs->gp;						\
     58	pr_reg[20] = regs->estatus;					\
     59	pr_reg[21] = regs->ea;						\
     60	pr_reg[22] = regs->orig_r7;					\
     61	{								\
     62		struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \
     63		pr_reg[23] = sw->r16;					\
     64		pr_reg[24] = sw->r17;					\
     65		pr_reg[25] = sw->r18;					\
     66		pr_reg[26] = sw->r19;					\
     67		pr_reg[27] = sw->r20;					\
     68		pr_reg[28] = sw->r21;					\
     69		pr_reg[29] = sw->r22;					\
     70		pr_reg[30] = sw->r23;					\
     71		pr_reg[31] = sw->fp;					\
     72		pr_reg[32] = sw->gp;					\
     73		pr_reg[33] = sw->ra;					\
     74	}								\
     75} while (0); }
     76
     77/* This yields a mask that user programs can use to figure out what
     78   instruction set this cpu supports.  */
     79
     80#define ELF_HWCAP	(0)
     81
     82/* This yields a string that ld.so will use to load implementation
     83   specific libraries for optimization.  This is more specific in
     84   intent than poking at uname or /proc/cpuinfo.  */
     85
     86#define ELF_PLATFORM  (NULL)
     87
     88#endif /* _ASM_NIOS2_ELF_H */