cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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entry.h (2644B)

      1/*
      2 * Copyright (C) 2010 Tobias Klauser <tklauser@distanz.ch>
      3 * Copyright (C) 2004 Microtronix Datacom Ltd.
      4 *
      5 * This file is subject to the terms and conditions of the GNU General Public
      6 * License. See the file "COPYING" in the main directory of this archive
      7 * for more details.
      8 */
      9
     10#ifndef _ASM_NIOS2_ENTRY_H
     11#define _ASM_NIOS2_ENTRY_H
     12
     13#ifdef __ASSEMBLY__
     14
     15#include <asm/processor.h>
     16#include <asm/registers.h>
     17#include <asm/asm-offsets.h>
     18
     19/*
     20 * Standard Nios2 interrupt entry and exit macros.
     21 * Must be called with interrupts disabled.
     22 */
     23.macro SAVE_ALL
     24	rdctl	r24, estatus
     25	andi	r24, r24, ESTATUS_EU
     26	beq	r24, r0, 1f /* In supervisor mode, already on kernel stack */
     27
     28	movia	r24, _current_thread	/* Switch to current kernel stack */
     29	ldw	r24, 0(r24)		/* using the thread_info */
     30	addi	r24, r24, THREAD_SIZE-PT_REGS_SIZE
     31	stw	sp, PT_SP(r24)		/* Save user stack before changing */
     32	mov	sp, r24
     33	br	2f
     34
     351 :	mov	r24, sp
     36	addi	sp, sp, -PT_REGS_SIZE	/* Backup the kernel stack pointer */
     37	stw	r24, PT_SP(sp)
     382 :	stw	r1, PT_R1(sp)
     39	stw	r2, PT_R2(sp)
     40	stw	r3, PT_R3(sp)
     41	stw	r4, PT_R4(sp)
     42	stw	r5, PT_R5(sp)
     43	stw	r6, PT_R6(sp)
     44	stw	r7, PT_R7(sp)
     45	stw	r8, PT_R8(sp)
     46	stw	r9, PT_R9(sp)
     47	stw	r10, PT_R10(sp)
     48	stw	r11, PT_R11(sp)
     49	stw	r12, PT_R12(sp)
     50	stw	r13, PT_R13(sp)
     51	stw	r14, PT_R14(sp)
     52	stw	r15, PT_R15(sp)
     53	stw	r2, PT_ORIG_R2(sp)
     54	stw	r7, PT_ORIG_R7(sp)
     55
     56	stw	ra, PT_RA(sp)
     57	stw	fp, PT_FP(sp)
     58	stw	gp, PT_GP(sp)
     59	rdctl	r24, estatus
     60	stw	r24, PT_ESTATUS(sp)
     61	stw	ea, PT_EA(sp)
     62.endm
     63
     64.macro RESTORE_ALL
     65	ldw	r1, PT_R1(sp)		/* Restore registers */
     66	ldw	r2, PT_R2(sp)
     67	ldw	r3, PT_R3(sp)
     68	ldw	r4, PT_R4(sp)
     69	ldw	r5, PT_R5(sp)
     70	ldw	r6, PT_R6(sp)
     71	ldw	r7, PT_R7(sp)
     72	ldw	r8, PT_R8(sp)
     73	ldw	r9, PT_R9(sp)
     74	ldw	r10, PT_R10(sp)
     75	ldw	r11, PT_R11(sp)
     76	ldw	r12, PT_R12(sp)
     77	ldw	r13, PT_R13(sp)
     78	ldw	r14, PT_R14(sp)
     79	ldw	r15, PT_R15(sp)
     80	ldw	ra, PT_RA(sp)
     81	ldw	fp, PT_FP(sp)
     82	ldw	gp, PT_GP(sp)
     83	ldw	r24, PT_ESTATUS(sp)
     84	wrctl	estatus, r24
     85	ldw	ea, PT_EA(sp)
     86	ldw	sp, PT_SP(sp)		/* Restore sp last */
     87.endm
     88
     89.macro	SAVE_SWITCH_STACK
     90	addi	sp, sp, -SWITCH_STACK_SIZE
     91	stw	r16, SW_R16(sp)
     92	stw	r17, SW_R17(sp)
     93	stw	r18, SW_R18(sp)
     94	stw	r19, SW_R19(sp)
     95	stw	r20, SW_R20(sp)
     96	stw	r21, SW_R21(sp)
     97	stw	r22, SW_R22(sp)
     98	stw	r23, SW_R23(sp)
     99	stw	fp, SW_FP(sp)
    100	stw	gp, SW_GP(sp)
    101	stw	ra, SW_RA(sp)
    102.endm
    103
    104.macro	RESTORE_SWITCH_STACK
    105	ldw	r16, SW_R16(sp)
    106	ldw	r17, SW_R17(sp)
    107	ldw	r18, SW_R18(sp)
    108	ldw	r19, SW_R19(sp)
    109	ldw	r20, SW_R20(sp)
    110	ldw	r21, SW_R21(sp)
    111	ldw	r22, SW_R22(sp)
    112	ldw	r23, SW_R23(sp)
    113	ldw	fp, SW_FP(sp)
    114	ldw	gp, SW_GP(sp)
    115	ldw	ra, SW_RA(sp)
    116	addi	sp, sp, SWITCH_STACK_SIZE
    117.endm
    118
    119#endif /* __ASSEMBLY__ */
    120#endif /* _ASM_NIOS2_ENTRY_H */