Kconfig (6264B)
1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.rst. 5# 6 7config OPENRISC 8 def_bool y 9 select ARCH_32BIT_OFF_T 10 select ARCH_HAS_DMA_SET_UNCACHED 11 select ARCH_HAS_DMA_CLEAR_UNCACHED 12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 13 select COMMON_CLK 14 select OF 15 select OF_EARLY_FLATTREE 16 select IRQ_DOMAIN 17 select GPIOLIB 18 select HAVE_ARCH_TRACEHOOK 19 select SPARSE_IRQ 20 select GENERIC_IRQ_CHIP 21 select GENERIC_IRQ_PROBE 22 select GENERIC_IRQ_SHOW 23 select GENERIC_IOMAP 24 select GENERIC_CPU_DEVICES 25 select HAVE_UID16 26 select GENERIC_ATOMIC64 27 select GENERIC_CLOCKEVENTS_BROADCAST 28 select GENERIC_SMP_IDLE_THREAD 29 select MODULES_USE_ELF_RELA 30 select HAVE_DEBUG_STACKOVERFLOW 31 select OR1K_PIC 32 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 33 select ARCH_USE_QUEUED_RWLOCKS 34 select OMPIC if SMP 35 select ARCH_WANT_FRAME_POINTERS 36 select GENERIC_IRQ_MULTI_HANDLER 37 select MMU_GATHER_NO_RANGE if MMU 38 select TRACE_IRQFLAGS_SUPPORT 39 40config CPU_BIG_ENDIAN 41 def_bool y 42 43config MMU 44 def_bool y 45 46config GENERIC_HWEIGHT 47 def_bool y 48 49config NO_IOPORT_MAP 50 def_bool y 51 52# For now, use generic checksum functions 53#These can be reimplemented in assembly later if so inclined 54config GENERIC_CSUM 55 def_bool y 56 57config STACKTRACE_SUPPORT 58 def_bool y 59 60config LOCKDEP_SUPPORT 61 def_bool y 62 63menu "Processor type and features" 64 65choice 66 prompt "Subarchitecture" 67 default OR1K_1200 68 69config OR1K_1200 70 bool "OR1200" 71 help 72 Generic OpenRISC 1200 architecture 73 74endchoice 75 76config DCACHE_WRITETHROUGH 77 bool "Have write through data caches" 78 default n 79 help 80 Select this if your implementation features write through data caches. 81 Selecting 'N' here will allow the kernel to force flushing of data 82 caches at relevant times. Most OpenRISC implementations support write- 83 through data caches. 84 85 If unsure say N here 86 87config OPENRISC_BUILTIN_DTB 88 string "Builtin DTB" 89 default "" 90 91menu "Class II Instructions" 92 93config OPENRISC_HAVE_INST_FF1 94 bool "Have instruction l.ff1" 95 default y 96 help 97 Select this if your implementation has the Class II instruction l.ff1 98 99config OPENRISC_HAVE_INST_FL1 100 bool "Have instruction l.fl1" 101 default y 102 help 103 Select this if your implementation has the Class II instruction l.fl1 104 105config OPENRISC_HAVE_INST_MUL 106 bool "Have instruction l.mul for hardware multiply" 107 default y 108 help 109 Select this if your implementation has a hardware multiply instruction 110 111config OPENRISC_HAVE_INST_DIV 112 bool "Have instruction l.div for hardware divide" 113 default y 114 help 115 Select this if your implementation has a hardware divide instruction 116 117config OPENRISC_HAVE_INST_CMOV 118 bool "Have instruction l.cmov for conditional move" 119 default n 120 help 121 This config enables gcc to generate l.cmov instructions when compiling 122 the kernel which in general will improve performance and reduce the 123 binary size. 124 125 Select this if your implementation has support for the Class II 126 l.cmov conistional move instruction. 127 128 Say N if you are unsure. 129 130config OPENRISC_HAVE_INST_ROR 131 bool "Have instruction l.ror for rotate right" 132 default n 133 help 134 This config enables gcc to generate l.ror instructions when compiling 135 the kernel which in general will improve performance and reduce the 136 binary size. 137 138 Select this if your implementation has support for the Class II 139 l.ror rotate right instruction. 140 141 Say N if you are unsure. 142 143config OPENRISC_HAVE_INST_RORI 144 bool "Have instruction l.rori for rotate right with immediate" 145 default n 146 help 147 This config enables gcc to generate l.rori instructions when compiling 148 the kernel which in general will improve performance and reduce the 149 binary size. 150 151 Select this if your implementation has support for the Class II 152 l.rori rotate right with immediate instruction. 153 154 Say N if you are unsure. 155 156config OPENRISC_HAVE_INST_SEXT 157 bool "Have instructions l.ext* for sign extension" 158 default n 159 help 160 This config enables gcc to generate l.ext* instructions when compiling 161 the kernel which in general will improve performance and reduce the 162 binary size. 163 164 Select this if your implementation has support for the Class II 165 l.exths, l.extbs, l.exthz and l.extbz size extend instructions. 166 167 Say N if you are unsure. 168 169endmenu 170 171config NR_CPUS 172 int "Maximum number of CPUs (2-32)" 173 range 2 32 174 depends on SMP 175 default "2" 176 177config SMP 178 bool "Symmetric Multi-Processing support" 179 help 180 This enables support for systems with more than one CPU. If you have 181 a system with only one CPU, say N. If you have a system with more 182 than one CPU, say Y. 183 184 If you don't know what to do here, say N. 185 186source "kernel/Kconfig.hz" 187 188config OPENRISC_NO_SPR_SR_DSX 189 bool "use SPR_SR_DSX software emulation" if OR1K_1200 190 default y 191 help 192 SPR_SR_DSX bit is status register bit indicating whether 193 the last exception has happened in delay slot. 194 195 OpenRISC architecture makes it optional to have it implemented 196 in hardware and the OR1200 does not have it. 197 198 Say N here if you know that your OpenRISC processor has 199 SPR_SR_DSX bit implemented. Say Y if you are unsure. 200 201config OPENRISC_HAVE_SHADOW_GPRS 202 bool "Support for shadow gpr files" if !SMP 203 default y if SMP 204 help 205 Say Y here if your OpenRISC processor features shadowed 206 register files. They will in such case be used as a 207 scratch reg storage on exception entry. 208 209 On SMP systems, this feature is mandatory. 210 On a unicore system it's safe to say N here if you are unsure. 211 212config CMDLINE 213 string "Default kernel command string" 214 default "" 215 help 216 On some architectures there is currently no way for the boot loader 217 to pass arguments to the kernel. For these architectures, you should 218 supply some command-line options at build time by entering them 219 here. 220 221menu "Debugging options" 222 223config JUMP_UPON_UNHANDLED_EXCEPTION 224 bool "Try to die gracefully" 225 default y 226 help 227 Now this puts kernel into infinite loop after first oops. Till 228 your kernel crashes this doesn't have any influence. 229 230 Say Y if you are unsure. 231 232config OPENRISC_ESR_EXCEPTION_BUG_CHECK 233 bool "Check for possible ESR exception bug" 234 default n 235 help 236 This option enables some checks that might expose some problems 237 in kernel. 238 239 Say N if you are unsure. 240 241endmenu 242 243endmenu