sigtramp.S (4280B)
1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Signal trampolines for 32 bit processes. 4 * 5 * Copyright (C) 2006 Randolph Chung <tausq@debian.org> 6 * Copyright (C) 2018-2022 Helge Deller <deller@gmx.de> 7 * Copyright (C) 2022 John David Anglin <dave.anglin@bell.net> 8 */ 9#include <asm/unistd.h> 10#include <linux/linkage.h> 11#include <generated/asm-offsets.h> 12 13 .text 14 15/* Gdb expects the trampoline is on the stack and the pc is offset from 16 a 64-byte boundary by 0, 4 or 5 instructions. Since the vdso trampoline 17 is not on the stack, we need a new variant with different offsets and 18 data to tell gdb where to find the signal context on the stack. 19 20 Here we put the offset to the context data at the start of the trampoline 21 region and offset the first trampoline by 2 instructions. Please do 22 not change the trampoline as the code in gdb depends on the following 23 instruction sequence exactly. 24 */ 25 .align 64 26 .word SIGFRAME_CONTEXT_REGS32 27 28/* The nop here is a hack. The dwarf2 unwind routines subtract 1 from 29 the return address to get an address in the middle of the presumed 30 call instruction. Since we don't have a call here, we artifically 31 extend the range covered by the unwind info by adding a nop before 32 the real start. 33 */ 34 nop 35 36 .globl __kernel_sigtramp_rt 37 .type __kernel_sigtramp_rt, @function 38__kernel_sigtramp_rt: 39 .proc 40 .callinfo FRAME=ASM_SIGFRAME_SIZE32,CALLS,SAVE_RP 41 .entry 42 43.Lsigrt_start = . - 4 440: ldi 0, %r25 /* (in_syscall=0) */ 45 ldi __NR_rt_sigreturn, %r20 46 ble 0x100(%sr2, %r0) 47 nop 48 491: ldi 1, %r25 /* (in_syscall=1) */ 50 ldi __NR_rt_sigreturn, %r20 51 ble 0x100(%sr2, %r0) 52 nop 53.Lsigrt_end: 54 .exit 55 .procend 56 .size __kernel_sigtramp_rt,.-__kernel_sigtramp_rt 57 58 59 .section .eh_frame,"a",@progbits 60 61/* This is where the mcontext_t struct can be found on the stack. */ 62#define PTREGS SIGFRAME_CONTEXT_REGS32 /* 32-bit process offset is -672 */ 63 64/* Register REGNO can be found at offset OFS of the mcontext_t structure. */ 65 .macro rsave regno,ofs 66 .byte 0x05 /* DW_CFA_offset_extended */ 67 .uleb128 \regno; /* regno */ 68 .uleb128 \ofs /* factored offset */ 69 .endm 70 71.Lcie: 72 .long .Lcie_end - .Lcie_start 73.Lcie_start: 74 .long 0 /* CIE ID */ 75 .byte 1 /* Version number */ 76 .stringz "zRS" /* NUL-terminated augmentation string */ 77 .uleb128 4 /* Code alignment factor */ 78 .sleb128 4 /* Data alignment factor */ 79 .byte 89 /* Return address register column, iaoq[0] */ 80 .uleb128 1 /* Augmentation value length */ 81 .byte 0x1b /* DW_EH_PE_pcrel | DW_EH_PE_sdata4. */ 82 .byte 0x0f /* DW_CFA_def_cfa_expresion */ 83 .uleb128 9f - 1f /* length */ 841: 85 .byte 0x8e /* DW_OP_breg30 */ 86 .sleb128 PTREGS 879: 88 .balign 4 89.Lcie_end: 90 91 .long .Lfde0_end - .Lfde0_start 92.Lfde0_start: 93 .long .Lfde0_start - .Lcie /* CIE pointer. */ 94 .long .Lsigrt_start - . /* PC start, length */ 95 .long .Lsigrt_end - .Lsigrt_start 96 .uleb128 0 /* Augmentation */ 97 98 /* General registers */ 99 rsave 1, 2 100 rsave 2, 3 101 rsave 3, 4 102 rsave 4, 5 103 rsave 5, 6 104 rsave 6, 7 105 rsave 7, 8 106 rsave 8, 9 107 rsave 9, 10 108 rsave 10, 11 109 rsave 11, 12 110 rsave 12, 13 111 rsave 13, 14 112 rsave 14, 15 113 rsave 15, 16 114 rsave 16, 17 115 rsave 17, 18 116 rsave 18, 19 117 rsave 19, 20 118 rsave 20, 21 119 rsave 21, 22 120 rsave 22, 23 121 rsave 23, 24 122 rsave 24, 25 123 rsave 25, 26 124 rsave 26, 27 125 rsave 27, 28 126 rsave 28, 29 127 rsave 29, 30 128 rsave 30, 31 129 rsave 31, 32 130 131 /* Floating-point registers */ 132 rsave 32, 42 133 rsave 33, 43 134 rsave 34, 44 135 rsave 35, 45 136 rsave 36, 46 137 rsave 37, 47 138 rsave 38, 48 139 rsave 39, 49 140 rsave 40, 50 141 rsave 41, 51 142 rsave 42, 52 143 rsave 43, 53 144 rsave 44, 54 145 rsave 45, 55 146 rsave 46, 56 147 rsave 47, 57 148 rsave 48, 58 149 rsave 49, 59 150 rsave 50, 60 151 rsave 51, 61 152 rsave 52, 62 153 rsave 53, 63 154 rsave 54, 64 155 rsave 55, 65 156 rsave 56, 66 157 rsave 57, 67 158 rsave 58, 68 159 rsave 59, 69 160 rsave 60, 70 161 rsave 61, 71 162 rsave 62, 72 163 rsave 63, 73 164 rsave 64, 74 165 rsave 65, 75 166 rsave 66, 76 167 rsave 67, 77 168 rsave 68, 78 169 rsave 69, 79 170 rsave 70, 80 171 rsave 71, 81 172 rsave 72, 82 173 rsave 73, 83 174 rsave 74, 84 175 rsave 75, 85 176 rsave 76, 86 177 rsave 77, 87 178 rsave 78, 88 179 rsave 79, 89 180 rsave 80, 90 181 rsave 81, 91 182 rsave 82, 92 183 rsave 83, 93 184 rsave 84, 94 185 rsave 85, 95 186 rsave 86, 96 187 rsave 87, 97 188 189 /* SAR register */ 190 rsave 88, 102 191 192 /* iaoq[0] return address register */ 193 rsave 89, 100 194 .balign 4 195.Lfde0_end: